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Re: [Xen-devel] [PATCH v3 04/15] xen/arm: vgic-v3: Correctly handle RAZ/WI registers

On Mon, 2015-02-16 at 14:50 +0000, Julien Grall wrote:
> Some of the registers are accessible via multiple size (see GICD_IPRIORITYR*).
> Those registers are incorrectly implemented when they should be RAZ. Only
> word-access size are currently allowed for them.
> The paragraph 5.3.1 in the GICv3 spec (PRD03-GENC-010745 24.0) indicates
> the different access-sizes supported for each register.
> The current vGICv3 driver is not ready for 32 bits guest and will
> require some rework. So, for now, only supporting access-size of a system not
> supporting aarch32.
> To avoid further issues, introduce different label following the access-size
> of the registers:
>     - read_as_zero_64 and write_ignore_64: Used for registers accessible
>     via a double-word.
>     - read_as_zero_32 and write_ignore_32: Used for registers accessible
>     via a word.
>     - read_as_zero: Used when we don't have to check the access size.
> The latter is used when the access size has already been checked in the
> register emulation and/or when the register offset is
> reserved/implementation defined.
> Signed-off-by: Julien Grall <julien.grall@xxxxxxxxxx>

Acked-by: Ian Campbell <ian.campbell@xxxxxxxxxx>

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