[Xen-devel] [PATCH 0/2] xen: arm: warn for gic and arch timer misconfiguration

[Ian Campbell <ian.campbell@xxxxxxxxxx>]

(Marc, you are just CCd FYI after our conversation last week, I don't
imagine you care much about the actual patches, so I didn't send them to
you, I can if you like)

In f688aec47c45 "xen/arm: Handle platforms with edge-triggered virtual
timer" we added a workaround for an issue seen on fast models with edge
triggered timer interrupts. Such a configuration doesn't make much sense
given the designed behaviour of the generic timers (the spec doesn't
explicitly say the IRQ must be level triggered, but the event condition
is described in terms of a >= inequality and it is strongly implied that
it behaves like a level triggered interrupt) and it has been bugging me
since.

I think I've finally gotten to the bottom of what is going on.

There are two overlapping issues, the first of which is that a number of
device tree files in the field incorrectly describe the arch timer
interrupts as edge-triggered. This includes the ones for models
published at http://www.linux-arm.org/git?p=arm-dts.git;a=summary and
https://github.com/ARM-software/arm-trusted-firmware as well as various
DTs for real hardware platforms shipped in linux.git (e.g.
apm-storm.dtsi is wrong).

The second issue is that on the models the GICD.ICFGR bits associated
with the timer PPI interrupts are actually writeable so that the
incorrect device tree description can be propagated to the real
hardware. It is IMPLEMENTATION DEFINED whether ICFGR is writeable for a
PPI and so far all the real platforms I've looked at (which is
admittedly not very many) do not allow the timer PPI configurations to
be written.

On the models (and so far nowhere else) these two issues combine to end
up with an edge triggered timer interrupt getting configured.

This little series adds warnings for both these cases in case we see
them on non-emulated platforms in the future.

Ian.



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