[Xen-devel] [PATCH 5/5] tools/mce: add more MCE types to xen-mceinj

[David Vrabel <david.vrabel@xxxxxxxxxx>]

Add a non-fatal MCE for AMD CPUs.

Add a fatal (PCC set) MCE for Intel CPUs.

Signed-off-by: David Vrabel <david.vrabel@xxxxxxxxxx>
Acked-by: Christoph Egger <chegger@xxxxxxxxx>
---
 tools/tests/mce-test/tools/xen-mceinj.c |   16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/tools/tests/mce-test/tools/xen-mceinj.c 
b/tools/tests/mce-test/tools/xen-mceinj.c
index d76aedb..91e313f 100644
--- a/tools/tests/mce-test/tools/xen-mceinj.c
+++ b/tools/tests/mce-test/tools/xen-mceinj.c
@@ -93,6 +93,22 @@ static struct mce_info mce_table[] = {
         .mci_misc = 0x86ull,
         .cmci = true,
     },
+    /* AMD L1 instruction cache data or tag parity. */
+    {
+        .description = "AMD L1 icache parity",
+        .mcg_stat = 0x5,
+        .bank = 1,
+        .mci_stat = 0x9400000000000151ull,
+        .mci_misc = 0x86ull,
+    },
+    /* LLC (Last Level Cache) EWB (Explicit Write Back) SRAO MCE */
+    {
+        .description = "MCE_SRAO_MEM (Fatal)",
+        .mcg_stat = 0x5,
+        .bank = 7,
+        .mci_stat = 0xBF2000008000017Aull,
+        .mci_misc = 0x86ull,
+    },
 };
 #define MCE_TABLE_SIZE (sizeof(mce_table)/sizeof(mce_table[0]))
 
-- 
1.7.10.4


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