[Xen-devel] [PATCH v6 0/5] vgic emulation and GICD_ITARGETSR

[Stefano Stabellini <stefano.stabellini@xxxxxxxxxxxxx>]

Hi all,
this patch series improves vgic emulation in relation to GICD_ITARGETSR,
and implements irq delivery to vcpus other than vcpu0.

vgic_enable_irqs and vgic_disable_irqs currently ignore the itarget
settings and just enable/disable irqs on the current vcpu. Fix their
behaviour to enable/disable irqs on the vcpu set by itarget, that is
vcpu0 for irq >= 32 initially.

Introduce a new vgic function called vgic_get_target_vcpu to retrieve
the right target vcpu (looking at itargets) and use it from do_IRQ.

Change the physical irq affinity to make physical irqs follow virtual
cpus migration.


Changes in v6:
- rebased on f7e46156a1c006a6eb5489e0227d39229eec316d;
- add ASSERT to _vgic_get_target_vcpu;
- add BUG_ON to vgic_distr_mmio_write;
- add in-code comment to _vgic_get_target_vcpu;
- move additional check on itargets writing from the second patch to
the first patch;
- sizeof(itargets) instead of 8*sizeof(itargets[0]);
- remove the unneeded cast of &target for find_first_bit;
- remove unnecessary casts to (const unsigned long *) to the arguments
of find_first_bit and find_next_bit;
- deal with migrating an irq that is inflight and still lr_pending;
- replace the dsb with smb_wmb and smb_rmb, use them to ensure the order
of accesses to GIC_IRQ_GUEST_QUEUED and GIC_IRQ_GUEST_MIGRATING;
- add in-code comments to vgic_vcpu_inject_spi and do_IRQ;
- assert that the guest irq is an SPI in vgic_vcpu_inject_spi;
- use vgic_get_target_vcpu instead of _vgic_get_target_vcpu in
arch_move_irqs;
- introduce sched_move_irqs.


Changes in v5:
- add "rename vgic_irq_rank to vgic_rank_offset";
- add "introduce vgic_rank_irq";
- improve in-code comments;
- use vgic_rank_irq;
- use bit masks to write-ignore GICD_ITARGETSR;
- introduce an version of vgic_get_target_vcpu that doesn't take the
rank lock;
- keep the rank lock while enabling/disabling irqs;
- use find_first_bit instead of find_next_bit;
- pass unsigned long to find_next_bit for alignment on aarch64;
- call vgic_get_target_vcpu instead of gic_add_to_lr_pending to add the
irq in the right inflight queue;
- add barrier and bit tests to make sure that vgic_migrate_irq and
gic_update_one_lr can run simultaneously on different cpus without
issues;
- rework the loop to identify the new vcpu when ITARGETSR is written;
- use find_first_bit instead of find_next_bit;
- prettify vgic_move_irqs;
- rename vgic_move_irqs to arch_move_irqs;
- introduce helper function irq_set_affinity.



Stefano Stabellini (5):
      xen/arm: observe itargets setting in vgic_enable_irqs and 
vgic_disable_irqs
      xen/arm: inflight irqs during migration
      xen/arm: support irq delivery to vcpu > 0
      xen/arm: physical irq follow virtual irq
      xen: introduce sched_move_irqs

 xen/arch/arm/gic.c           |   46 +++++++++--
 xen/arch/arm/irq.c           |    5 +-
 xen/arch/arm/vgic.c          |  179 ++++++++++++++++++++++++++++++++++++++----
 xen/common/schedule.c        |   12 ++-
 xen/include/asm-arm/domain.h |    4 +
 xen/include/asm-arm/gic.h    |    4 +
 xen/include/asm-x86/irq.h    |    2 +
 7 files changed, 228 insertions(+), 24 deletions(-)

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