Re: [Xen-devel] [ARM:PATCH v2 1/1] Pass the timer clock-frequency to DOM0

[Julien Grall <julien.grall@xxxxxxxxxx>]

On 13/04/14 21:48, Suriyan Ramasami wrote:
> On Sun, Apr 13, 2014 at 1:20 PM, Julien Grall <julien.grall@xxxxxxxxxx> wrote:
> fanta's patch to get the CPU up in NS HYP mode is in hardkernel's git
> repository ->
>   
> https://github.com/hardkernel/u-boot/commit/56e5bdcb95d41f9236554de0578b0017a9f232a5
>
> Hence, it would appear that the SPL BL2 code is entered in NS HYP mode.
>
> Also, BL1 I believe is signed and encrypted - hence no access. BL2 can
> be signed and that is how currently we are entering in NS HYP.
Thanks for the explanation.

By any chance, do you know if the Arndale octa (exynos 5420) also bring 
CPU in HYP mode the same way?
> Apparently the tzsw can be signed too, and hence, I was thinking of
> modifying a current smc call to have it set the CNTFRQ, which I
> believe will be in monitor mode.
We had the same issue on the Arndale last year. Luckily u-boot were 
booting in Secure mode.
It would be great to have a firmware that correctly configure the Arch 
timer (according the ARM ARM). But I bet the Arndale octa will have the 
same issue. So we will have to handle this such configuration in Xen.
Can you send a new version with remarks make previously?

Regards,

--
Julien Grall

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