Re: [Xen-devel] [ARM:PATCH v2 1/1] Pass the timer clock-frequency to DOM0

[Suriyan Ramasami <suriyan.r@xxxxxxxxx>]

On Sun, Apr 13, 2014 at 1:20 PM, Julien Grall <julien.grall@xxxxxxxxxx> wrote:
> Hello,
>
>
> On 13/04/14 20:28, Suriyan Ramasami wrote:
>>
>> On Fri, Apr 11, 2014 at 9:32 AM, Julien Grall <julien.grall@xxxxxxxxxx>
>> wrote:
>>>
>>> Hello,
>>>
>>> On 04/11/2014 05:05 PM, Suriyan Ramasami wrote:
>>>>
>>>> On Tue, Apr 1, 2014 at 4:12 AM, Ian Campbell <Ian.Campbell@xxxxxxxxxx>
>>>> wrote:
>>>>>
>>>>> On Fri, 2014-03-28 at 14:04 +0000, Julien Grall wrote:
>>>>>>
>>>>>> That made me think that this is the only board with this issue. I
>>>>>> would
>>>>>> definitely prefer to fix the clock frequency in U-boot. The bootloader
>>>>>> should respect the ARM ARM (see B.8.1.1):
>>>>>>
>>>>>> "The CNTFRQ register is UNKNOWN at reset, and therefore the counter
>>>>>> frequency must written to CNTFRQ as part
>>>>>> of the system boot process."
>>>>>
>>>>>
>>>>> Yes, Suriyan, please exhaust this avenue of attack (fixing u-boot on
>>>>> the
>>>>> platform) first.
>>>>>
>>>> Thank you gentlemen for your comments.
>>>> The problem with this board is that the uboot is not entered in secure
>>>> mode, and hence the mcr indstruction to set the ARCH timer frequency
>>>> cannot be executed in u-boot.
>>>
>>>
>>> If so, what is the state of the CPU when it jumps to U-boot?
>>> The CPU has to be either in secure mode or hyp mode.
>>> AFAIK, if it's NS you won't be able to go in hyp mode, unless crash the
>>> CPU...
>>>
>> The CPU is in HYP mode when it jumps to U-boot.
>
>
> I'm lost...
>
> From my understanding (i.e what I read on the web). For your case you use a
> modified U-boot/SPL, right?
>
Correct - the one in hardlernel's git with a modification done by fanta.

> If so, without this modification, in which state U-boot is booting? What are
> the CPU states along the different bl (1,2)?
>
> Did you try this u-boot: https://github.com/medicalwei/u-boot-odroidxu-hyp?
> FYI I don't have any odroid XU. I'm trying to understand
Haven't tried this one.
>
Sorry Julien! Not my intent.
This post possibly has the details that you are looking for:
http://forum.odroid.com/viewtopic.php?f=64&t=2778&start=40#p31301

fanta's patch to get the CPU up in NS HYP mode is in hardkernel's git
repository ->
 
https://github.com/hardkernel/u-boot/commit/56e5bdcb95d41f9236554de0578b0017a9f232a5

Hence, it would appear that the SPL BL2 code is entered in NS HYP mode.

Also, BL1 I believe is signed and encrypted - hence no access. BL2 can
be signed and that is how currently we are entering in NS HYP.
Apparently the tzsw can be signed too, and hence, I was thinking of
modifying a current smc call to have it set the CNTFRQ, which I
believe will be in monitor mode.

> Regards,
>
> --
> Julien Grall

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