[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] Re: [Xen-devel] Is: 0xCF8 on extended config space instead of MCONF? Was:Re: IBM HS20 Xen 4.1 and 4.2 Critical Interrupt - Front panel NMI crash
On Fri, Oct 04, 2013 at 06:31:37PM +0200, Trenta sis wrote: > Hi, > > With Xen 4.0 kernel used was 2.6.32, default kernel Debain 6 (Squeeze) > Thanks So if you swap either kernel or hypervisor do you see this? Meaning if you run with Xen 4.2 + 2.6.32 or Xen 4.0 + current kernel. > > 2013/9/30 Konrad Rzeszutek Wilk <konrad.wilk@xxxxxxxxxx> > > > > Hdlr: 00151743 HI Fatal Error, HI_FERR/NERR Value= 0020 > > > 27 I Blade_09 09/08/13 13:25:17 0x806f0013 Chassis, (NMI State) > > diagnostic > > > interrupt > > > 28 E Blade_09 09/08/13 13:25:12 0x10000002 SMI Hdlr: 00151743 HI Fatal > > > Error, HI_FERR/NERR Value= 0020 > > > > Doing a simple Google search on HI_FERR tells me that it is: > > > > > > http://www.intel.com/content/dam/doc/datasheet/e7525-memory-controller-hub-datasheet.pdf > > > > and that > > 3.6.14 HI_FERR â Hub Interface First Error Register (D0:F1) > > > > has something in it. The value is 0020 (is that decimal or hex?). If it is > > decimal it is then 10100, which is bit 2 and 4: > > > > bit 2: > > > > HI Internal Parity Error Detected. This bit is sticky through reset. System > > software clears this bit by writing a â1â to the location. > > 0 = No Internal Parity error detected. > > 1 = MCH HI bridge has detected an Internal Parity error. Non-fatal. > > > > and bit 4: > > HI Data Parity Error Detected. This bit is sticky through reset. System > > software > > clears this bit by writing a â1â to the location. > > 0 = No HI data parity error. > > 1 = MCH has detected a parity error on the data phase of a HI transaction. > > > > > > > > But that is unlikely as these are 'non-fatal'. So if this is hex, then it > > would > > be bit 5, which is: > > > > Enhanced Configuration Access Error. This bit is sticky through reset. > > System > > software clears this bit by writing a â1â to the location. > > 0 = No Enhanced Configuration Access error > > 1 = A PCI Express* Enhanced Configuration access was mistakenly targeting > > the legacy interface. Fatal > > > > > > That sounds more like it. So we touched a PCIe Enhanced Configuration > > (MMCONFIG?) > > using the legacy interface (cf8?). > > > > Jan, any thoughts? Is there a particular bug-fix we are missing in Xen 4.1 > > or Xen 4.2 > > for this? Xen 4.0 seems to work. > > > > Trenta, > > > > When you used Xen 4.0 did you use the same kernel as with Xen 4.1 or Xen > > 4.2? > > _______________________________________________ Xen-devel mailing list Xen-devel@xxxxxxxxxxxxx http://lists.xen.org/xen-devel
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