[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] [Xen-devel] [PATCH] Re: Question about set up the HCTR at arm32/head.S.
Hi, At 17:42 +0900 on 27 Mar (1364406168), Gihun Jung wrote: > It described "PT walks are write-back, no-write-allocate in both cache > level": load 0x80002500 to r0. > At 4rd position of 0x800025000 (i.e. 5 = b0101), that is my question > point. According to armv7 architecture manual, that bits should be b11 > respectively for both cache levels to enable "write-back, > no-write-allocate", but, in the code, it seems set up to "write-back, > write-allocate" for both cache levels. I am not sure which one is > correct: comment or code? Well spotted - the code is correct. Thanks, Tim. -------- arm: fix comment in HTCR setup. Reported-by: Gihun Jung <gihun.jung@xxxxxxxxx> Signed-off-by: Tim Deegan <tim@xxxxxxx> diff --git a/xen/arch/arm/arm32/head.S b/xen/arch/arm/arm32/head.S index db3baa0..f2f581d 100644 --- a/xen/arch/arm/arm32/head.S +++ b/xen/arch/arm/arm32/head.S @@ -189,7 +189,7 @@ skip_bss: /* Set up the HTCR: * PT walks use Outer-Shareable accesses, - * PT walks are write-back, no-write-allocate in both cache levels, + * PT walks are write-back, write-allocate in both cache levels, * Full 32-bit address space goes through this table. */ ldr r0, =0x80002500 mcr CP32(r0, HTCR) diff --git a/xen/arch/arm/arm64/head.S b/xen/arch/arm/arm64/head.S index b7ab251..bbde419 100644 --- a/xen/arch/arm/arm64/head.S +++ b/xen/arch/arm/arm64/head.S @@ -173,7 +173,7 @@ skip_bss: * PASize -- 4G * Top byte is used * PT walks use Outer-Shareable accesses, - * PT walks are write-back, no-write-allocate in both cache levels, + * PT walks are write-back, write-allocate in both cache levels, * Full 64-bit address space goes through this table. */ ldr x0, =0x80802500 msr tcr_el2, x0 _______________________________________________ Xen-devel mailing list Xen-devel@xxxxxxxxxxxxx http://lists.xen.org/xen-devel
|
Lists.xenproject.org is hosted with RackSpace, monitoring our |