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[Xen-devel] Question about set up the HCTR at arm32/head.S.

Hi Developers!

When I read Xen ARM source code, I found some curious point to want to
ask about it.
At arm32/head.S, there are lines to set up the HCTR. According to
written comments and codes:

/* Set up the HTCR:
 * PT walks use Outer-Shareable accesses,
 * PT walks are write-back, no-write-allocate in both cache levels,
 * Full 32-bit address space goes through this table. */

 ldr   r0, =0x80002500
 mcr   CP32(r0, HTCR)

It described "PT walks are write-back, no-write-allocate in both cache
level": load 0x80002500 to r0.
At 4rd position of 0x800025000 (i.e. 5 = b0101), that is my question
point. According to armv7 architecture manual, that bits should be b11
respectively for both cache levels to enable "write-back,
no-write-allocate", but, in the code, it seems set up to "write-back,
write-allocate" for both cache levels. I am not sure which one is
correct: comment or code?

Best Regards,
Gihun Jung

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