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Re: [Xen-devel] [PATCH V2] Add CPUID bit mask for Performance Counter Extension
Sorry. I missed this email from the mailing list thread. Please see my
answer below.
On 3/6/2013 4:10 PM, Konrad Rzeszutek Wilk wrote:
On Tue, Mar 05, 2013 at 05:01:26PM -0600, suravee.suthikulpanit@xxxxxxx wrote:
Adding CPUID bit mask for Performance Counter Extension. The extended
counter MSRs are already virtualized. This bit mask allows the initialization
code to properly detect the feature and enable the use of counters.
Just to be clear, to make use of this, the guest config has to have
cpuid="perfctr_core"
Guest should not need to config anything. The patch allows the host's
CPUID bit to be passed on to guest. However, users can also force the
CPUID bits to set/clear by specifying:
cpuid = "host,perfctr_core=0"
Is this something that is the same for Intel hardware? Meaning is the
code path in xl the same for enabling performance counters on Intel?
This is AMD specific CPUID flag, and therefore is specified in the
"amd_xc_cpuid_policy".
Suravee.
Signed-off-by: Jacob Shin <Jacob.Shin@xxxxxxx>
Submitted-by: Suravee Suthikulpanit <suravee.suthikulpanit@xxxxxxx>
---
Changelog:
V2:
* Add commit log message
tools/libxc/xc_cpufeature.h | 1 +
tools/libxc/xc_cpuid_x86.c | 1 +
tools/libxl/libxl_cpuid.c | 1 +
3 files changed, 3 insertions(+)
diff --git a/tools/libxc/xc_cpufeature.h b/tools/libxc/xc_cpufeature.h
index c464e3a..c804af3 100644
--- a/tools/libxc/xc_cpufeature.h
+++ b/tools/libxc/xc_cpufeature.h
@@ -125,6 +125,7 @@
#define X86_FEATURE_NODEID_MSR 19 /* NodeId MSR */
#define X86_FEATURE_TBM 21 /* trailing bit manipulations */
#define X86_FEATURE_TOPOEXT 22 /* topology extensions CPUID leafs */
+#define X86_FEATURE_PERFCTR_CORE 23 /* core performance counter extensions */
/* Intel-defined CPU features, CPUID level 0x00000007:0 (ebx) */
#define X86_FEATURE_FSGSBASE 0 /* {RD,WR}{FS,GS}BASE instructions */
diff --git a/tools/libxc/xc_cpuid_x86.c b/tools/libxc/xc_cpuid_x86.c
index 17efc0f..c269468 100644
--- a/tools/libxc/xc_cpuid_x86.c
+++ b/tools/libxc/xc_cpuid_x86.c
@@ -112,6 +112,7 @@ static void amd_xc_cpuid_policy(
bitmaskof(X86_FEATURE_XOP) |
bitmaskof(X86_FEATURE_FMA4) |
bitmaskof(X86_FEATURE_TBM) |
+ bitmaskof(X86_FEATURE_PERFCTR_CORE) |
bitmaskof(X86_FEATURE_LWP));
regs[3] &= (0x0183f3ff | /* features shared with 0x00000001:EDX */
(is_pae ? bitmaskof(X86_FEATURE_NX) : 0) |
diff --git a/tools/libxl/libxl_cpuid.c b/tools/libxl/libxl_cpuid.c
index d17fdd6..f3f1265 100644
--- a/tools/libxl/libxl_cpuid.c
+++ b/tools/libxl/libxl_cpuid.c
@@ -147,6 +147,7 @@ int libxl_cpuid_parse_config(libxl_cpuid_policy_list
*cpuid, const char* str)
{"vme", 0x00000001, NA, CPUID_REG_EDX, 1, 1},
{"fpu", 0x00000001, NA, CPUID_REG_EDX, 0, 1},
{"topoext", 0x80000001, NA, CPUID_REG_ECX, 22, 1},
+ {"perfctr_core", 0x80000001, NA, CPUID_REG_ECX, 23, 1},
{"tbm", 0x80000001, NA, CPUID_REG_ECX, 21, 1},
{"nodeid", 0x80000001, NA, CPUID_REG_ECX, 19, 1},
{"fma4", 0x80000001, NA, CPUID_REG_ECX, 16, 1},
--
1.7.10.4
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