Re: [Xen-devel] [PATCH 29/38] arm: delay enabling data-cache until paging enabled.

[Ian Campbell <Ian.Campbell@xxxxxxxxxx>]

On Thu, 2012-06-07 at 14:59 +0100, Tim Deegan wrote:
> At 20:04 +0100 on 01 Jun (1338581061), Ian Campbell wrote:
> > On Fri, 2012-06-01 at 18:05 +0100, Tim Deegan wrote:
> > > At 15:39 +0000 on 01 Jun (1338565198), Ian Campbell wrote:
> > > > With enough warnings enabled the model seemed to be complaining that 
> > > > pages
> > > > cached before paging was enabled had been mapped with to inconsistent 
> > > > sets of
> > > > attributes. I'm not convinced that isn't a model issue, nor am I 
> > > > convinced
> > > > this has really fixed anything, but it seems sensible enough.
> > > 
> > > This might be what breaks secondary CPU bringup: pagetables built by CPU
> > > 0 may not have been flushed all the way to RAM when CPU 1 comes up, and
> > > CPU 1 isn't participating in cache coherence protocols when it
> > > starts to need them.
> > 
> > The issue here is the lack of the necessary flush, rather than this
> > change particularly, right?
> 
> It turns out to be much more prosaic - the patch to delete the identity
> mapping from the boot pagetables was scuppering non-boot CPUs.
> 
> So this is OK, but can I suggest this to tidy it up?

Seems sensible. With this and Stefano's spelling fix it becomes:

>From fe5304fb1d1e6e607b125ccfbdc59b25e1d84b34 Mon Sep 17 00:00:00 2001
From: Ian Campbell <ian.campbell@xxxxxxxxxx>
Date: Mon, 14 May 2012 15:49:27 +0100
Subject: [PATCH] arm: enable data-cache at the same time as enabling the MMU,
 not before

With enough warnings enabled the model seemed to be complaining that pages
cached before paging was enabled had been mapped with to inconsistent sets of
attributes. I'm not convinced that isn't a model issue, nor am I convinced
this has really fixed anything, but it seems sensible enough.

Signed-off-by: Ian Campbell <ian.campbell@xxxxxxxxxx>
---
 xen/arch/arm/head.S |    7 ++++---
 1 files changed, 4 insertions(+), 3 deletions(-)

diff --git a/xen/arch/arm/head.S b/xen/arch/arm/head.S
index 9a7714a..cdbe011 100644
--- a/xen/arch/arm/head.S
+++ b/xen/arch/arm/head.S
@@ -148,10 +148,11 @@ hyp:
         * Exceptions in LE ARM,
         * Low-latency IRQs disabled,
         * Write-implies-XN disabled (for now),
-        * I-cache and d-cache enabled,
+        * D-cache disabled (for now),
+        * I-cache enabled,
         * Alignment checking enabled,
         * MMU translation disabled (for now). */
-       ldr   r0, =(HSCTLR_BASE|SCTLR_A|SCTLR_C)
+       ldr   r0, =(HSCTLR_BASE|SCTLR_A)
        mcr   CP32(r0, HSCTLR)
 
        /* Write Xen's PT's paddr into the HTTBR */
@@ -210,7 +211,7 @@ pt_ready:
 
        ldr   r1, =paging            /* Explicit vaddr, not RIP-relative */
        mrc   CP32(r0, HSCTLR)
-       orr   r0, r0, #0x1           /* Add in the MMU enable bit */
+       orr   r0, r0, #(SCTLR_M|SCTLR_C) /* Enable MMU and D-cache */
        dsb                          /* Flush PTE writes and finish reads */
        mcr   CP32(r0, HSCTLR)       /* now paging is enabled */
        isb                          /* Now, flush the icache */
-- 
1.7.9.1




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