Re: [Xen-devel] [PATCH 29/38] arm: delay enabling data-cache until paging enabled.

[Ian Campbell <Ian.Campbell@xxxxxxxxxx>]

On Fri, 2012-06-01 at 18:05 +0100, Tim Deegan wrote:
> At 15:39 +0000 on 01 Jun (1338565198), Ian Campbell wrote:
> > With enough warnings enabled the model seemed to be complaining that pages
> > cached before paging was enabled had been mapped with to inconsistent sets 
> > of
> > attributes. I'm not convinced that isn't a model issue, nor am I convinced
> > this has really fixed anything, but it seems sensible enough.
> 
> This might be what breaks secondary CPU bringup: pagetables built by CPU
> 0 may not have been flushed all the way to RAM when CPU 1 comes up, and
> CPU 1 isn't participating in cache coherence protocols when it
> starts to need them.

The issue here is the lack of the necessary flush, rather than this
change particularly, right?

> OTOH, if that's the case, it's surprising that CPU 1 passes the boot
> gate.  I'll look into it next week, x86/mm workload permitting. 

Sounds good!

I tried to test SMP yesterday but ut turned out all the models I thought
were SMP enabled were actual UP Only, not sure how/when that happened!

Cheers,
Ian.

> 
> Cheers,
> 
> Tim.
> 
> > Signed-off-by: Ian Campbell <ian.campbell@xxxxxxxxxx>
> > ---
> >  xen/arch/arm/head.S |    9 +++++++--
> >  1 files changed, 7 insertions(+), 2 deletions(-)
> > 
> > diff --git a/xen/arch/arm/head.S b/xen/arch/arm/head.S
> > index 9a7714a..71197af 100644
> > --- a/xen/arch/arm/head.S
> > +++ b/xen/arch/arm/head.S
> > @@ -148,10 +148,11 @@ hyp:
> >      * Exceptions in LE ARM,
> >      * Low-latency IRQs disabled,
> >      * Write-implies-XN disabled (for now),
> > -    * I-cache and d-cache enabled,
> > +    * D-cache diabled (for now),
> > +    * I-cache enabled,
> >      * Alignment checking enabled,
> >      * MMU translation disabled (for now). */
> > -   ldr   r0, =(HSCTLR_BASE|SCTLR_A|SCTLR_C)
> > +   ldr   r0, =(HSCTLR_BASE|SCTLR_A)
> >     mcr   CP32(r0, HSCTLR)
> >  
> >     /* Write Xen's PT's paddr into the HTTBR */
> > @@ -217,6 +218,10 @@ pt_ready:
> >     mov   pc, r1                 /* Get a proper vaddr into PC */
> >  paging:
> >  
> > +   mrc   CP32(r0, HSCTLR)       /* Now enable data cache */
> > +   orr   r0, r0, #(SCTLR_C)
> > +   mcr   CP32(r0, HSCTLR)
> > +
> >  #ifdef EARLY_UART_ADDRESS
> >     /* Recover the UART address in the new address space. */
> >     lsl   r11, #11
> > -- 
> > 1.7.9.1
> > 
> > 
> > _______________________________________________
> > Xen-devel mailing list
> > Xen-devel@xxxxxxxxxxxxx
> > http://lists.xen.org/xen-devel



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