[Xen-devel] [PATCH 04 of 10] arm: Handle booting on SMP platforms

[Tim Deegan <tim@xxxxxxx>]

# HG changeset patch
# User Tim Deegan <tim@xxxxxxx>
# Date 1330018799 0
# Node ID 8f322ab538572e1a12c8ed716ddd5cb4c122e9ed
# Parent  437ad1207a175c9ad376871f3f4c075dbcd5b6e6
arm: Handle booting on SMP platforms

Make all non-boot CPUs wait forever instead of trying to boot in parallel.

Signed-off-by: Tim Deegan <tim@xxxxxxx>

diff -r 437ad1207a17 -r 8f322ab53857 xen/arch/arm/head.S
--- a/xen/arch/arm/head.S       Thu Feb 23 17:39:59 2012 +0000
+++ b/xen/arch/arm/head.S       Thu Feb 23 17:39:59 2012 +0000
@@ -61,6 +61,19 @@ start:
        add   r8, r10                /* r8 := paddr(DTB) */
 #endif
 
+       /* Are we the boot CPU? */
+       mrc   CP32(r0, MPIDR)
+       tst   r0, #(1<<31)           /* Multiprocessor extension supported? */
+       beq   boot_cpu
+       tst   r0, #(1<<30)           /* Uniprocessor system? */
+       bne   boot_cpu
+       bics  r0, r0, #(0xff << 24)  /* Ignore flags */
+       beq   boot_cpu               /* If all other fields are 0, we win */
+
+1:     wfi
+       b     1b
+       
+boot_cpu:
 #ifdef EARLY_UART_ADDRESS
        /* Say hello */
        ldr   r11, =EARLY_UART_ADDRESS  /* r11 := UART base address */
diff -r 437ad1207a17 -r 8f322ab53857 xen/include/asm-arm/cpregs.h
--- a/xen/include/asm-arm/cpregs.h      Thu Feb 23 17:39:59 2012 +0000
+++ b/xen/include/asm-arm/cpregs.h      Thu Feb 23 17:39:59 2012 +0000
@@ -91,6 +91,7 @@
 /* Coprocessor 15 */
 
 /* CP15 CR0: CPUID and Cache Type Registers */
+#define MPIDR           p15,0,c0,c0,5   /* Multiprocessor Affinity Register */
 #define ID_PFR0         p15,0,c0,c1,0   /* Processor Feature Register 0 */
 #define ID_PFR1         p15,0,c0,c1,1   /* Processor Feature Register 1 */
 #define ID_DFR0         p15,0,c0,c1,2   /* Debug Feature Register 0 */

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