Re: [Xen-devel] [PATCH 04 of 16] amd iommu: Enable ppr log

["Jan Beulich" <JBeulich@xxxxxxxx>]

>>> On 23.12.11 at 12:29, Wei Wang <wei.wang2@xxxxxxx> wrote:
> # HG changeset patch
> # User Wei Wang <wei.wang2@xxxxxxx>
> # Date 1324569381 -3600
> # Node ID 33f88c76776c318eea74b8fc1ba467389407ad57
> # Parent  07f338ae663242ba9080f1ab84298894783da3e2
> amd iommu: Enable ppr log.
> IOMMUv2 writes peripheral page service request (PPR) records into ppr log
> to report DMA page request from ATS devices to OS.
> 
> Signed-off-by: Wei Wang <wei.wang2@xxxxxxx>
> 
> diff -r 07f338ae6632 -r 33f88c76776c xen/drivers/passthrough/amd/iommu_init.c
> --- a/xen/drivers/passthrough/amd/iommu_init.c        Thu Dec 22 16:56:17 
> 2011 +0100
> +++ b/xen/drivers/passthrough/amd/iommu_init.c        Thu Dec 22 16:56:21 
> 2011 +0100
> @@ -178,6 +178,34 @@ static void register_iommu_event_log_in_
>      writel(entry, iommu->mmio_base+IOMMU_EVENT_LOG_BASE_HIGH_OFFSET);
>  }
>  
> +static void register_iommu_ppr_log_in_mmio_space(struct amd_iommu *iommu)
> +{
> +    u64 addr_64, addr_lo, addr_hi;

The latter two should be u32.

> +    u32 power_of2_entries;
> +    u32 entry;
> +
> +    ASSERT ( iommu->ppr_log.buffer );
> +
> +    addr_64 = (u64)virt_to_maddr(iommu->ppr_log.buffer);

Pointless cast?

> +    addr_lo = addr_64 & DMA_32BIT_MASK;

DMA_32BIT_MASK is clearly not meant to be used here (and if addr_lo
was of type u32, a plain assignment would be all that's needed here).

Jan

> +    addr_hi = addr_64 >> 32;
> +
> +    entry = 0;
> +    iommu_set_addr_lo_to_reg(&entry, addr_lo >> PAGE_SHIFT);
> +    writel(entry, iommu->mmio_base + IOMMU_PPR_LOG_BASE_LOW_OFFSET);
> +
> +    power_of2_entries = get_order_from_bytes(iommu->ppr_log.alloc_size) +
> +                        IOMMU_PPR_LOG_POWER_OF2_ENTRIES_PER_PAGE;
> +
> +    entry = 0;
> +    iommu_set_addr_hi_to_reg(&entry, addr_hi);
> +    set_field_in_reg_u32(power_of2_entries, entry,
> +                        IOMMU_PPR_LOG_LENGTH_MASK,
> +                        IOMMU_PPR_LOG_LENGTH_SHIFT, &entry);
> +    writel(entry, iommu->mmio_base + IOMMU_PPR_LOG_BASE_HIGH_OFFSET);
> +}
> +
> +
>  static void set_iommu_translation_control(struct amd_iommu *iommu,
>                                                   int enable)
>  {



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