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[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] Re: [Xen-devel] [PATCH 02 of 16] amd iommu: Introduces new helper functions to simplify iommu bitwise operations
>>> On 23.12.11 at 12:29, Wei Wang <wei.wang2@xxxxxxx> wrote:
> --- a/xen/drivers/passthrough/amd/iommu_cmd.c Thu Dec 22 16:56:10 2011 +0100
> +++ b/xen/drivers/passthrough/amd/iommu_cmd.c Thu Dec 22 16:56:14 2011 +0100
> @@ -33,10 +33,8 @@ static int queue_iommu_command(struct am
> if ( ++tail == iommu->cmd_buffer.entries )
> tail = 0;
>
> - head = get_field_from_reg_u32(readl(iommu->mmio_base +
> - IOMMU_CMD_BUFFER_HEAD_OFFSET),
> - IOMMU_CMD_BUFFER_HEAD_MASK,
> - IOMMU_CMD_BUFFER_HEAD_SHIFT);
> + head = iommu_get_rb_pointer(readl(iommu->mmio_base +
> + IOMMU_CMD_BUFFER_HEAD_OFFSET));
> if ( head != tail )
> {
> cmd_buffer = (u32 *)(iommu->cmd_buffer.buffer +
> @@ -55,11 +53,9 @@ static int queue_iommu_command(struct am
>
> static void commit_iommu_command_buffer(struct amd_iommu *iommu)
> {
> - u32 tail;
> + u32 tail = 0;
>
> - set_field_in_reg_u32(iommu->cmd_buffer.tail, 0,
> - IOMMU_CMD_BUFFER_TAIL_MASK,
> - IOMMU_CMD_BUFFER_TAIL_SHIFT, &tail);
> + iommu_set_rb_pointer(&tail, iommu->cmd_buffer.tail);
> writel(tail, iommu->mmio_base+IOMMU_CMD_BUFFER_TAIL_OFFSET);
> }
>
Afaict with these two changes IOMMU_CMD_BUFFER_{HEAD,TAIL}_{MASK,SHIFT}
are unused, so please remove them.
> --- a/xen/drivers/passthrough/amd/iommu_init.c Thu Dec 22 16:56:10
> 2011 +0100
> +++ b/xen/drivers/passthrough/amd/iommu_init.c Thu Dec 22 16:56:14
> 2011 +0100
> @@ -106,21 +106,21 @@ static void register_iommu_dev_table_in_
> u64 addr_64, addr_lo, addr_hi;
> u32 entry;
>
> + ASSERT( iommu->dev_table.buffer );
> +
> addr_64 = (u64)virt_to_maddr(iommu->dev_table.buffer);
> addr_lo = addr_64 & DMA_32BIT_MASK;
> addr_hi = addr_64 >> 32;
>
> - set_field_in_reg_u32((u32)addr_lo >> PAGE_SHIFT, 0,
> - IOMMU_DEV_TABLE_BASE_LOW_MASK,
> - IOMMU_DEV_TABLE_BASE_LOW_SHIFT, &entry);
> + entry = 0;
> + iommu_set_addr_lo_to_reg(&entry, addr_lo >> PAGE_SHIFT);
While I didn't check, I suspect the same applies to the old definitions
here and further down in this same file.
> --- a/xen/include/asm-x86/hvm/svm/amd-iommu-proto.h Thu Dec 22 16:56:10
> 2011 +0100
> +++ b/xen/include/asm-x86/hvm/svm/amd-iommu-proto.h Thu Dec 22 16:56:14
> 2011
> +0100
> @@ -191,5 +191,85 @@ static inline int iommu_has_feature(stru
> return 0;
> return !!(iommu->features & (1U << bit));
> }
> +/* access tail or head pointer of ring buffer */
> +#define IOMMU_RING_BUFFER_PTR_MASK 0x0007FFF0
> +#define IOMMU_RING_BUFFER_PTR_SHIFT 4
I suppose these (and the others below) really belong into
amd-iommu-defs.h?
Jan
> +static inline uint32_t iommu_get_rb_pointer(uint32_t reg)
> +{
> + return get_field_from_reg_u32(reg, IOMMU_RING_BUFFER_PTR_MASK,
> + IOMMU_RING_BUFFER_PTR_SHIFT);
> +}
> +
> +static inline void iommu_set_rb_pointer(uint32_t *reg, uint32_t val)
> +{
> + set_field_in_reg_u32(val, *reg, IOMMU_RING_BUFFER_PTR_MASK,
> + IOMMU_RING_BUFFER_PTR_SHIFT, reg);
> +}
> +
> +/* access device field from iommu cmd */
> +#define IOMMU_CMD_DEVICE_ID_MASK 0x0000FFFF
> +#define IOMMU_CMD_DEVICE_ID_SHIFT 0
> +
> +static inline uint16_t iommu_get_devid_from_cmd(uint32_t cmd)
> +{
> + return get_field_from_reg_u32(cmd, IOMMU_CMD_DEVICE_ID_MASK,
> + IOMMU_CMD_DEVICE_ID_SHIFT);
> +}
> +
> +static inline void iommu_set_devid_to_cmd(uint32_t *cmd, uint16_t id)
> +{
> + set_field_in_reg_u32(id, *cmd, IOMMU_CMD_DEVICE_ID_MASK,
> + IOMMU_CMD_DEVICE_ID_SHIFT, cmd);
> +}
> +
> +/* access address field from iommu cmd */
> +#define IOMMU_CMD_ADDR_LOW_MASK 0xFFFFF000
> +#define IOMMU_CMD_ADDR_LOW_SHIFT 12
> +#define IOMMU_CMD_ADDR_HIGH_MASK 0xFFFFFFFF
> +#define IOMMU_CMD_ADDR_HIGH_SHIFT 0
> +
> +static inline uint32_t iommu_get_addr_lo_from_cmd(uint32_t cmd)
> +{
> + return get_field_from_reg_u32(cmd, IOMMU_CMD_ADDR_LOW_MASK,
> + IOMMU_CMD_ADDR_LOW_SHIFT);
> +}
> +
> +static inline uint32_t iommu_get_addr_hi_from_cmd(uint32_t cmd)
> +{
> + return get_field_from_reg_u32(cmd, IOMMU_CMD_ADDR_LOW_MASK,
> + IOMMU_CMD_ADDR_HIGH_SHIFT);
> +}
> +
> +#define iommu_get_devid_from_event iommu_get_devid_from_cmd
> +
> +/* access iommu base addresses from mmio regs */
> +#define IOMMU_REG_BASE_ADDR_BASE_LOW_MASK 0xFFFFF000
> +#define IOMMU_REG_BASE_ADDR_LOW_SHIFT 12
> +#define IOMMU_REG_BASE_ADDR_HIGH_MASK 0x000FFFFF
> +#define IOMMU_REG_BASE_ADDR_HIGH_SHIFT 0
> +
> +static inline void iommu_set_addr_lo_to_reg(uint32_t *reg, uint32_t addr)
> +{
> + set_field_in_reg_u32(addr, *reg, IOMMU_REG_BASE_ADDR_BASE_LOW_MASK,
> + IOMMU_REG_BASE_ADDR_LOW_SHIFT, reg);
> +}
> +
> +static inline void iommu_set_addr_hi_to_reg(uint32_t *reg, uint32_t addr)
> +{
> + set_field_in_reg_u32(addr, *reg, IOMMU_REG_BASE_ADDR_HIGH_MASK,
> + IOMMU_REG_BASE_ADDR_HIGH_SHIFT, reg);
> +}
> +
> +static inline uint32_t iommu_get_addr_lo_from_reg(uint32_t reg)
> +{
> + return get_field_from_reg_u32(reg, IOMMU_REG_BASE_ADDR_BASE_LOW_MASK,
> + IOMMU_REG_BASE_ADDR_LOW_SHIFT);
> +}
> +
> +static inline uint32_t iommu_get_addr_hi_from_reg(uint32_t reg)
> +{
> + return get_field_from_reg_u32(reg, IOMMU_REG_BASE_ADDR_HIGH_MASK,
> + IOMMU_REG_BASE_ADDR_HIGH_SHIFT);
> +}
>
> #endif /* _ASM_X86_64_AMD_IOMMU_PROTO_H */
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