[Xen-changelog] [xen master] arm: traps: handle SMC32 in check_conditional_instr()

[patchbot@xxxxxxx]

commit 7f86858186f4932ceba91f731337e0ef536d6cd0
Author:     Volodymyr Babchuk <volodymyr_babchuk@xxxxxxxx>
AuthorDate: Wed Aug 16 21:44:57 2017 +0300
Commit:     Stefano Stabellini <sstabellini@xxxxxxxxxx>
CommitDate: Fri Aug 18 10:27:56 2017 -0700

    arm: traps: handle SMC32 in check_conditional_instr()
    
    On ARMv8 architecture we need to ensure that conditional check was passed
    for a trapped SMC instruction that originates from AArch32 state
    (ARM DDI 0487B.a page D7-2271).
    Thus, we should not skip it while checking HSR.EC value.
    
    For this type of exception special coding of HSR.ISS is used. There is
    additional flag (CCKNOWNPASS) to be checked before performing standard
    handling of CCVALID and COND fields.
    
    Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@xxxxxxxx>
    Reviewed-by: Julien Grall <julien.grall@xxxxxxx>
    Signed-off-by: Stefano Stabellini <sstabellini@xxxxxxxxxx>
---
 xen/arch/arm/traps.c | 19 ++++++++++++++++++-
 1 file changed, 18 insertions(+), 1 deletion(-)

diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c
index eae2212..2e92223 100644
--- a/xen/arch/arm/traps.c
+++ b/xen/arch/arm/traps.c
@@ -1716,8 +1716,25 @@ static int check_conditional_instr(struct cpu_user_regs 
*regs,
     unsigned long cpsr, cpsr_cond;
     int cond;
 
+    /*
+     * SMC32 instruction case is special. Under SMC32 we mean SMC
+     * instruction on ARMv7 or SMC instruction originating from
+     * AArch32 state on ARMv8.
+     * On ARMv7 it will be trapped only if it passed condition check
+     * (ARM DDI 0406C.c page B3-1431), but we need to check condition
+     * flags on ARMv8 (ARM DDI 0487B.a page D7-2271).
+     * Encoding for HSR.ISS on ARMv8 is backwards compatible with ARMv7:
+     * HSR.ISS is defined as UNK/SBZP on ARMv7 which means, that it
+     * will be read as 0. This includes CCKNOWNPASS field.
+     * If CCKNOWNPASS == 0 then this was an unconditional instruction or
+     * it has passed conditional check (ARM DDI 0487B.a page D7-2272).
+     */
+    if ( hsr.ec == HSR_EC_SMC32 && hsr.smc32.ccknownpass == 0 )
+        return 1;
+
     /* Unconditional Exception classes */
-    if ( hsr.ec == HSR_EC_UNKNOWN || hsr.ec >= 0x10 )
+    if ( hsr.ec == HSR_EC_UNKNOWN ||
+         (hsr.ec >= 0x10 && hsr.ec != HSR_EC_SMC32) )
         return 1;
 
     /* Check for valid condition in hsr */
--
generated by git-patchbot for /home/xen/git/xen.git#master

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