[Xen-changelog] [xen master] arm: traps: handle unknown exceptions in check_conditional_instr()

[patchbot@xxxxxxx]

commit 8604e12694fef08494c2e15fd85acd92dddd8111
Author:     Volodymyr Babchuk <volodymyr_babchuk@xxxxxxxx>
AuthorDate: Wed Aug 16 21:44:56 2017 +0300
Commit:     Stefano Stabellini <sstabellini@xxxxxxxxxx>
CommitDate: Fri Aug 18 10:27:53 2017 -0700

    arm: traps: handle unknown exceptions in check_conditional_instr()
    
    According to ARM architecture reference manual (ARM DDI 0487B.a page 
D7-2259,
    ARM DDI 0406C.c page B3-1426), exception with unknown reason (HSR.EC == 0)
    has no valid bits in HSR (apart from HSR.EC), so we can't check if that was
    caused by conditional instruction. We need to assume that it is 
unconditional.
    
    Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@xxxxxxxx>
    Acked-by: Julien Grall <julien.grall@xxxxxxx>
    Signed-off-by: Stefano Stabellini <sstabellini@xxxxxxxxxx>
---
 xen/arch/arm/traps.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c
index c07999b..eae2212 100644
--- a/xen/arch/arm/traps.c
+++ b/xen/arch/arm/traps.c
@@ -1717,7 +1717,7 @@ static int check_conditional_instr(struct cpu_user_regs 
*regs,
     int cond;
 
     /* Unconditional Exception classes */
-    if ( hsr.ec >= 0x10 )
+    if ( hsr.ec == HSR_EC_UNKNOWN || hsr.ec >= 0x10 )
         return 1;
 
     /* Check for valid condition in hsr */
--
generated by git-patchbot for /home/xen/git/xen.git#master

_______________________________________________
Xen-changelog mailing list
Xen-changelog@xxxxxxxxxxxxx
https://lists.xenproject.org/xen-changelog