Re: [XenARM] Cortex-A15 Virtualization Support and IOMMU

[See-Hwan Yoo <seehwan.yoo@xxxxxxxxx>]

Hi,
I am very glad to hear the news on recent updates.

Could you tell me where the starting point is? do you have any doc. to follow?

BTW, Is IOMMU separatedly supported from SMMU? or integrated one?
please be aware that there are several implementations (e.g. omap,
msm, tegra, etc.) that includes iommu out there.

2011/12/2 Stefano Stabellini <stefano.stabellini@xxxxxxxxxxxxx>:
> On Fri, 2 Dec 2011, Adi Habusha wrote:
>> Hi,
>>
>> I was happy to hear you have release initial virtualization support for
>> ARM Cortex A15 using the LPAE, GIC and Generic Timer.
>> Can you please elaborate how does DMA address space is managed? Is it
>> Guest OS Physical Address (IPA) or system Physical Address?
>> If Guest OS (IPA), is there any level of support to IOMMU (based on ARM
>> SMMU architecture)
>
> At the moment we are mapping the MMIO regions 1:1, so IPA == PA.
> However we are looking forward to introducing SMMU support in the future.
>
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