[PATCH] arm/entry: set x0 before cache maintenance.

[Jianyong Wu <jianyong.wu@xxxxxxx>]

There is a long standing issue in entry code of arm that x0 is not
set before using it in clean_and_invalidate_dcache_range. This error
can be caught by kvm and result in core dump.
Here, x0 is set to the location where stores dtb before cache maintain.

Signed-off-by: Jianyong Wu <jianyong.wu@xxxxxxx>
---
 plat/kvm/arm/entry64.S    | 5 +++++
 plat/kvm/arm/link64.lds.S | 1 +
 2 files changed, 6 insertions(+)

diff --git a/plat/kvm/arm/entry64.S b/plat/kvm/arm/entry64.S
index c4de334..2c36d6d 100644
--- a/plat/kvm/arm/entry64.S
+++ b/plat/kvm/arm/entry64.S
@@ -92,6 +92,11 @@ ENTRY(_libkvmplat_entry)
        add x27, x26, x17
        add x27, x27, #__STACK_SIZE
        sub x1, x27, x25
+
+       /*
+        * set x0 as the start of ram address.
+        */
+       ldr x0, = _start_ram_addr;
        bl clean_and_invalidate_dcache_range
 
        /* Disable the MMU and D-Cache. */
diff --git a/plat/kvm/arm/link64.lds.S b/plat/kvm/arm/link64.lds.S
index 4f8fcc3..cfe1454 100644
--- a/plat/kvm/arm/link64.lds.S
+++ b/plat/kvm/arm/link64.lds.S
@@ -56,6 +56,7 @@ SECTIONS {
 
        /* Place DTB binary at the beginning of the RAM */
        _dtb = .;
+       _start_ram_addr = .;
        . = . + DTB_RESERVED_SIZE;
 
        /* Code */
-- 
2.17.1