Re: [Minios-devel] [UNIKRAFT PATCHv4 15/43] uk/arch: Add necessary header files for Arm64

[Simon Kuenzer <simon.kuenzer@xxxxxxxxx>]

Hi all,

On 13.07.2018 11:36, Julien Grall wrote:
> Hi,
>
> On 13/07/18 10:13, Wei Chen wrote:
> > > > +#ifndef __UKARCH_LCPU_H__
> > > > +#error Do not include this header directly
> > > > +#endif
> > > > +
> > > > +struct __regs {
> > > > +    /* Generic Purpose registers, from x0 ~ x29 */
> > > > +    unsigned long x[30];
> > > > +
> > > > +    /* Link Register (x30) */
> > > > +    unsigned long lr;
> > > > +
> > > > +    /* Exception Link Register */
> > > > +    unsigned long elr_el1;
> > > > +
> > > > +    /* Processor State Register */
> > > > +    unsigned long spsr_el1;
> > > > +
> > > > +    /* Exception Status Register */
> > > > +    unsigned long esr_el1;
> > > > +
> > > > +    /* Stack Pointer */
> > > > +    unsigned long sp;
> > > > +};
> > > > +
> > > > +#define isb()   __asm__ __volatile("isb" ::: "memory")
> > > What is this intended for?
> > This is for instruction memory barrier.
> Just to clarify, isb is not a memory barrier ;). It is an instruction 
> synchronization barrier. Any instructions in program order after the isb 
> will only be fetched from cache/memory once the instruction has 
> completed. This is used to ensure the effect of modification such as TLB 
> invalidation, system registers have been taken into account.
> I am not aware of any equivalent on x86.
>
> Cheers,
Nice, now I learned something more about Arm. ;-) I like the 
explicitness of the architecture. It is giving you much more control 
about when and what should happen on the hardware.
My question: Is it clear for an Arm developer what "isb()" is or should 
we add a short comment to this definition?
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