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Re: [Xen-devel] [PATCH 4/4] amd iommu: Large io page support - implementation
At 18:00 +0000 on 07 Dec (1291744845), Keir Fraser wrote:
> Cc'ing Tim -- he could advise how plausible it is to find other available
> bits to move the p2m types to.
PAE Xen we need to use bits 9-11 because there are no other bits
available. On 64-bit we could just shift all the type bits up by three;
I think there's plenty of space above bit 52 for all the types we need.
Even on PAE we really only need to store a p2m type in leaf nodes (l1
entries and superpage entries) so bits 9-11 are free on internal nodes.
I don't understand why the iommu tables have a level stored in every
entry, though - is that a hardware requirement?
> Also I'm not sure whether the p2m tables ever
> get used as host pagetables these days (e.g., when guest has CR0.PG=0). That
> could affect how difficult it is to mess with the p2m format.
They never get used for PG=0 any more, we have a page in the firmware
with a 1-1 4GB mapping instead. But they do get used as pagetables in
order to use a linear mapping to read the p2m quickly.
> If it's possible, though, it's probably worth pursuing. Sharing the tables
> uses less memory, and could be less complicated code too.
Yep, sounds like a great idea.
> On 07/12/2010 11:20, "Wei Wang2" <wei.wang2@xxxxxxx> wrote:
> > Hi Allen,
> > Actually, each amd iommu pde entry uses bit 9-11 to encode next page table
> > level, but these bits are also used as AVL bits by p2m table to encode
> > different page types...So, it might not be quite easy to share NPT table
> > with
> > amd iommu unless we change p2m table encoding for this first.
> > Thanks,
> > Wei
> > On Tuesday 07 December 2010 01:47:22 Kay, Allen M wrote:
> >> Hi Wei,
> >> My understanding is that both EPT/NPT already supports 2M and 1G page
> >> sizes. If this is true and if NPT supports the same page table format as
> >> AMD iommu, shouldn't iommu 2M and 1G support just a matter of pointing
> >> iommu page table pointer to NPT page table of the same guest OS thus
> >> sharing the same page table between NPT and AMD iommu?
> >> This should save a lot code changes in iommu code. We just need to flush
> >> iommu page table in IOTLB at appropriate places.
> >> Allen
> >> -----Original Message-----
> >> From: xen-devel-bounces@xxxxxxxxxxxxxxxxxxx
> >> [mailto:xen-devel-bounces@xxxxxxxxxxxxxxxxxxx] On Behalf Of Wei Wang2 Sent:
> >> Friday, December 03, 2010 8:04 AM
> >> To: xen-devel@xxxxxxxxxxxxxxxxxxx
> >> Subject: [Xen-devel] [PATCH 4/4] amd iommu: Large io page support -
> >> implementation
> >> This is the implementation.
> >> Thanks,
> >> We
> >> Signed-off-by: Wei Wang <wei.wang2@xxxxxxx>
> >> --
> >> Legal Information:
> >> Advanced Micro Devices GmbH
> >> Sitz: Dornach, Gemeinde Aschheim,
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> >> Geschäftsführer:
> >> Alberto Bozzo, Andrew Bowd
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Tim Deegan <Tim.Deegan@xxxxxxxxxx>
Principal Software Engineer, Xen Platform Team
Citrix Systems UK Ltd. (Company #02937203, SL9 0BG)
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