[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] Re: [Xen-users] perf hardware event on ARM64
On Mon, Nov 2, 2015 at 10:33 AM, Ian Campbell <ian.campbell@xxxxxxxxxx> wrote:
Thanks, Ian. I have two questions. 1. What's the reason why perf is not supported by Xen on ARM? Is it because of what you've mentioned before? "The core issue with PMU is that Xen currently does not know how to context switch the relevant state when changing guests. " 2. I'm trying to make it work in a limited environment (pined, 1:1) on Dom0. It's a bit awkward (and I'm sorry) to ask questions about something not supported, but even a simple comment will be really helpful! The problem I have is that Xen is getting FIQ for pmu overflow interrupts. It looks like group 0 interrupts are enabled and FIQen bit is not set, by this line inÂxen/arch/arm/gic-v2.c writel_gicc(GICC_CTL_ENABLE|GICC_CTL_EOI, GICC_CTLR); So, I think FIQ should not come, can it? Instead of getting panic because of FIQ, I tried to make it run as normal IRQ by modifying entry.S, and routing FIQ to normal IRQ function by calling do_trap_fiq. System didn't go panic, but it was just hanging there. I'm a bit lost where to start to fix this. I think getting IRQ instead of FIQ is the first step. Do you have any suggestions? Thanks, Jintack Â
_______________________________________________ Xen-users mailing list Xen-users@xxxxxxxxxxxxx http://lists.xen.org/xen-users
|
Lists.xenproject.org is hosted with RackSpace, monitoring our |