Re: [Xen-users] Debugging DomU

[Julien Grall <julien.grall@xxxxxxxxxx>]

On 21/05/2015 00:48, Chris (Christopher) Brand wrote:
> Hi Julien,

Hi Chris,

Sorry for the late answer.

>>   I was asking if the kernel already setup his PT and enable pagination.
> 
> No, I don't believe it's gotten that far.
> 
>> The important CONFIG_* that should be enable are:
> [snip]
> All of these were enabled except for one:
>>          - CONFIG_ARCH_VIRT
> 
> I tried enabling that one, and it still ended up in the same state (as far as 
> I can tell), but I saw two messages from Xen, too:
> (XEN) traps.c:1757:d1v0 mcr p14, 0, r1, cr0, cr5, 0 @ 0x40e4e1f8

If I'm not mistaken this is DBGDTRTXint register.

> (XEN) traps.c:1759:d1v0 unhandled 32-bit cp14 access 0xa

When a register is not handled by Xen, an undef instruction
will be injected to the guest.

Currently Xen use a dummy implementation of Debug registers
which let the guest think it's not possible to use hardware
debugging.

Although, it looks like we miss some registers when it was
implemented.

AFAICT DBDGDTRTXint register should be handled WI/RAZ. Can
you give a try to the patch below?

============
diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c
index 47d6cef..ec56359 100644
--- a/xen/arch/arm/traps.c
+++ b/xen/arch/arm/traps.c
@@ -1921,6 +1921,7 @@ static void do_cp14_32(struct cpu_user_regs *regs, const 
union hsr hsr)
     case HSR_CPREG32(DBGWCR0):
     case HSR_CPREG32(DBGBVR1):
     case HSR_CPREG32(DBGBCR1):
+    case HSR_CPREG32(DBGDTRTXint): /* Share the same opcode as DBGDTRRXint */
         return handle_raz_wi(regs, r, cp32.read, hsr, 1);

     /*
diff --git a/xen/include/asm-arm/cpregs.h b/xen/include/asm-arm/cpregs.h
index e5cb00c..80276fc 100644
--- a/xen/include/asm-arm/cpregs.h
+++ b/xen/include/asm-arm/cpregs.h
@@ -82,6 +82,8 @@
 #define DBGWCR0         p14,0,c0,c0,7   /* Watchpoint Control 0 */
 #define DBGBVR1         p14,0,c0,c1,4   /* Breakpoint Value 1 */
 #define DBGBCR1         p14,0,c0,c1,5   /* Breakpoint Control 1 */
+#define DBGDTRTXint     p14,0,c0,c5,0   /* Target To Host Data Transfer 
Internal */
+#define DBGDTRRXint     p14,0,c0,c5,0   /* Host To Target Data Transfer 
Internal */
 #define DBGOSLAR        p14,0,c1,c0,4   /* OS Lock Access */
 #define DBGOSLSR        p14,0,c1,c1,4   /* OS Lock Status Register */
 #define DBGOSDLR        p14,0,c1,c3,4   /* OS Double Lock */
===============

Regards,

-- 
Julien Grall

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