Re: [XenPPC] Re: Add Function to completely flush the I-Cache for a processor

[Jimi Xenidis <jimix@xxxxxxxxxxxxxx>]

On Oct 2, 2006, at 6:18 PM, Hollis Blanchard wrote:

> On Mon, 2006-10-02 at 22:02 +0000, Xen patchbot-xenppc-unstable wrote:
> > +void cpu_flush_icache(void)
> > +{
> > +    union hid1 hid1;
> > +    ulong flags;
> > +    ulong ra;
> >
> > +    local_irq_save(flags);
> > +
> > +    /* uses special processor mode that forces a real address  
> > match */
> > +    hid1.word = mfhid1();
> > +    hid1.bits.en_icbi = 1;
> > +    mthid1(hid1.word);
> icbi uses effective addresses, not real addresses.
correct.
I'll fix it so it uses 'ea' not 'ra'.

> The docs say that bit
> is "Enable forced Instruction Cache Block Invalidate (icbi) match  
> mode,"
> which I don't understand.
See section "3.3.1Flushing the L1 I-Cache"

icbi finds "the line" by EA then consults the MMU for an RA to match  
the 1 of 4 entries in the line.
HID1[en_icbi] will cause:
  "all directory lookups on behalf of an icbi act as though there  
was a real address match"
invalidating the whole line.


> Are you saying that bit makes the invalidate work on real addresses
> rather than effective? Why would we want that?
We don't.

> Doesn't this loop work just fine with effective addresses?
Apparently not, My understanding is, the original (EA,RA)  
relationship established by the domain is unknown to the hypervisor,  
so we would get the index but not match on the RA.
> > +    for (ra = 0; ra < cpu_caches.isize; ra += cpu_caches.iline_size)
> > +        icbi(ra);
> > +
> > +    sync();
> > +
> > +    hid1.bits.en_icbi = 0;
> > +    mthid1(hid1.word);
> > +
> > +    local_irq_save(flags);
> > +}
> ^^^ local_irq_restore
good catch, thanks

-JX

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