[Xen-ia64-devel] [PATCH] make translate_phy_pte() static

[Kouya Shimura <kouya@xxxxxxxxxxxxxx>]

make translate_phy_pte() static.
second argument pte doesn't need to be a pointer.

Signed-off-by: Kouya Shimura <kouya@xxxxxxxxxxxxxx>

diff -r 0a2ee4279326 xen/arch/ia64/vmx/vtlb.c
--- a/xen/arch/ia64/vmx/vtlb.c  Wed Feb 13 10:37:18 2008 -0700
+++ b/xen/arch/ia64/vmx/vtlb.c  Thu Feb 14 20:03:32 2008 +0900
@@ -23,6 +23,7 @@
 #include <asm/vmx_vcpu.h>
 #include <asm/vmx_phy_mode.h>
 
+static u64 translate_phy_pte(VCPU *v, u64 pte, u64 itir, u64 va);
 static thash_data_t *__alloc_chain(thash_cb_t *);
 
 static inline void cch_mem_init(thash_cb_t *hcb)
@@ -182,7 +183,7 @@ void thash_vhpt_insert(VCPU *v, u64 pte,
     u64 phy_pte, psr;
     ia64_rr mrr;
 
-    phy_pte = translate_phy_pte(v, &pte, itir, va);
+    phy_pte = translate_phy_pte(v, pte, itir, va);
     mrr.rrval = ia64_get_rr(va);
 
     if (itir_ps(itir) >= mrr.ps && VMX_MMU_MODE(v) != VMX_MMU_PHY_D) {
@@ -509,22 +510,19 @@ void thash_purge_entries_remote(VCPU *v,
     vhpt_purge(v, va, ps);
 }
 
-u64 translate_phy_pte(VCPU *v, u64 *pte, u64 itir, u64 va)
+static u64 translate_phy_pte(VCPU *v, u64 pte, u64 itir, u64 va)
 {
     u64 ps, ps_mask, paddr, maddr;
-//    ia64_rr rr;
     union pte_flags phy_pte;
 
     ps = itir_ps(itir);
     ps_mask = ~((1UL << ps) - 1);
-    phy_pte.val = *pte;
-    paddr = *pte;
-    paddr = ((paddr & _PAGE_PPN_MASK) & ps_mask) | (va & ~ps_mask);
+    phy_pte.val = pte;
+    paddr = ((pte & _PAGE_PPN_MASK) & ps_mask) | (va & ~ps_mask);
     maddr = lookup_domain_mpa(v->domain, paddr, NULL);
-    if (maddr & GPFN_IO_MASK) {
-        *pte |= VTLB_PTE_IO;
+    if (maddr & GPFN_IO_MASK)
         return -1;
-    }
+
     /* Ensure WB attribute if pte is related to a normal mem page,
      * which is required by vga acceleration since qemu maps shared
      * vram buffer with WB.
@@ -532,8 +530,6 @@ u64 translate_phy_pte(VCPU *v, u64 *pte,
     if (phy_pte.ma != VA_MATTR_NATPAGE)
         phy_pte.ma = VA_MATTR_WB;
 
-//    rr.rrval = ia64_get_rr(va);
-//    ps = rr.ps;
     maddr = ((maddr & _PAGE_PPN_MASK) & PAGE_MASK) | (paddr & ~PAGE_MASK);
     phy_pte.ppn = maddr >> ARCH_PAGE_SHIFT;
     return phy_pte.val;
@@ -553,12 +549,12 @@ int thash_purge_and_insert(VCPU *v, u64 
     ps = itir_ps(itir);
     mrr.rrval = ia64_get_rr(ifa);
 
-    phy_pte = translate_phy_pte(v, &pte, itir, ifa);
+    phy_pte = translate_phy_pte(v, pte, itir, ifa);
 
     vtlb_purge(v, ifa, ps);
     vhpt_purge(v, ifa, ps);
 
-    if (pte & VTLB_PTE_IO) {
+    if (phy_pte == -1) {
         vtlb_insert(v, pte, itir, ifa);
         return 1;
     }
diff -r 0a2ee4279326 xen/include/asm-ia64/vmmu.h
--- a/xen/include/asm-ia64/vmmu.h       Wed Feb 13 10:37:18 2008 -0700
+++ b/xen/include/asm-ia64/vmmu.h       Thu Feb 14 20:02:42 2008 +0900
@@ -198,7 +198,6 @@ extern unsigned long fetch_code(struct v
 extern unsigned long fetch_code(struct vcpu *vcpu, u64 gip, IA64_BUNDLE 
*pbundle);
 extern void emulate_io_inst(struct vcpu *vcpu, u64 padr, u64 ma);
 extern int vhpt_enabled(struct vcpu *vcpu, uint64_t vadr, vhpt_ref_t ref);
-extern u64 translate_phy_pte(struct vcpu *v, u64 *pte, u64 itir, u64 va);
 extern void thash_vhpt_insert(struct vcpu *v, u64 pte, u64 itir, u64 ifa,
                               int type);
 extern u64 guest_vhpt_lookup(u64 iha, u64 *pte);

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