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RE: [Xen-ia64-devel] [PATCH] [Resend]Enable hash vtlb


  • To: "Tristan Gingold" <Tristan.Gingold@xxxxxxxx>, <xen-ia64-devel@xxxxxxxxxxxxxxxxxxx>
  • From: "Xu, Anthony" <anthony.xu@xxxxxxxxx>
  • Date: Mon, 10 Apr 2006 20:24:11 +0800
  • Delivery-date: Mon, 10 Apr 2006 05:24:24 -0700
  • List-id: Discussion of the ia64 port of Xen <xen-ia64-devel.lists.xensource.com>
  • Thread-index: AcZckpW2HVl7eMu+RE+dHDc8FXPVIQAAmj7Q
  • Thread-topic: [Xen-ia64-devel] [PATCH] [Resend]Enable hash vtlb

Hi Tristan

Thanks for your comments

>From: Tristan Gingold 
>Sent: 2006年4月10日 19:37
>Le Vendredi 07 Avril 2006 21:02, Xu, Anthony a écrit :
>> Hash vTLB is intended to address SMP scalability for large system.
>I don't really understand this.
>
>From my point of view, your patches add 3 changes:
>* VHPT is per VP (and not LP).
>* Collision chains
>* itc large pages correctly handled.
>
>I won't discuss itc large page.  This bug could be also fixed in the current
>implementation.
We are in the same page about this.

>
>I don't think per VP VHPT will improve scalability.  At least not when each LP
>is assigned to only one VCPU.
>
When each LP is assigned to only one VCPU, per VP VHPT is same with per LP VHPT.
But if there are several VCPUs(they belong to different domains) running on one 
LP, per VP VHPT definitely will improve scalability.

>Collision chains may improve performances.  My only concern is wether or not
>collision chains will well support SMP-g.
>
Because it is per VP VHPT, seems it is easier to support SMP-g.

In my mind, it's more natural to use IPI to emulate ptc.g.

I know your method of emulating "ptc.g" is efficient, and works well by far.

I saw below in SDM3 "Only one global purge transaction may be issued at a time
by all processors, the operation is undefined otherwise. Software is responsible
for enforcing this restriction"
Seems you need to add a global lock to serialize "ptc.g" on all processor.
If ptc.g instruction is blocked by lock, may other VCPUs in the same domain use 
the old tlb entries?

I will add an option, thus collision chain can be configured. Then there are two
method to support SMP-g coexisting in VMM.
1. VHPT without collision chain + your approach of emulating ptc.g
2. VHPT with collision chain + IPI approach of emulating ptc.g.
Let performance data choose better one.


>
>(BTW, I'd prefer a command line option such as vtlb=vp-vhpt or vtlb=lp-vhpt
>rather than a compile-time option).
Yes, we can do that. But I don't think it's necessary, because if one LP only 
runs one VCPU, VP-VHPT is equal to LP-VHPT.


Thanks,
Anthony
>
>Tristan.

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