[PATCH 0/2] x86/cpu: TSC handling adjustments

[Roger Pau Monne <roger@xxxxxxxxxxxxxx>]

Hello,

The fist patch fixes a bug if started with TSC_AUX != 0, as then the
cached value won't match the hardware one.

Second patch fixes handling of TSC_ADJUST and TSC offset for HVM
domains, in an attempt to make it consistent with hardware behavior.

Thanks, Roger.

Roger Pau Monne (2):
  x86/cpu: keep cached TSC_AUX state coherent with hardware
  x86/hvm: sync APs TSC with the BSP at creation only

 xen/arch/x86/acpi/power.c |  3 +++
 xen/arch/x86/cpu/common.c |  5 +++++
 xen/arch/x86/hvm/domain.c |  5 -----
 xen/arch/x86/hvm/hvm.c    | 19 +++++++++++--------
 xen/arch/x86/hvm/save.c   | 34 ++++++++++++++++++++++++++++++++--
 xen/arch/x86/time.c       |  5 ++---
 6 files changed, 53 insertions(+), 18 deletions(-)

-- 
2.55.0