Re: [PATCH] x86/vlapic: Don't change ICR on x2APIC SELF_IPI write

[Andrew Cooper <andrew.cooper3@xxxxxxxxxx>]

On 19/10/2026 3:26 pm, Teddy Astie wrote:
> The Intel SDM (Vol 3A-13.12.11, June 2026) says
>
>> The semantics of sending a self-IPI via the SELF IPI register
>> are identical to sending a self targeted edge triggered fixed
>> interrupt with the specified vector.
> However, this is not expected to alter the ICR register.

Having spoken to Intel, all Core/P-core's implement SELF_IPI using ICR,
so do mutate the value.

More recent Atom/E-core designs implement SELF_IPI differently, and do
not mutate ICR.  From the testing I performed in Gitlab-CI, "More
recent" is at least AlderLake and later, so Gracemont cores.

Either way, this is conformation that both behaviours are legitimate,
and it is certainly not a "bugfix" to change the behaviour.

There might be enough reason to change the behaviour, as the Atom
behaviour "feels" cleaner, and because it reduces the work we need to do
in the SELF_IPI path, but a justification needs to be along these lines,
not in terms of being a bugfix.

Perhaps a better reason to make the change is because the VT-x
architecture appears to not overwrite ICR, even on Core designs, and
this would be a behavioural difference between APICV or not.

> Fix the Xen behavior by sending the Self-IPI directly instead of
> emulating it by modifying ICR register.
>
> Fixes: 21c4d089ba2a ("x86 hvm: x2APIC emulation")
> Assisted-by: Claude Fable 5.1
> Signed-off-by: Teddy Astie <teddy.astie@xxxxxxxxxx>
> ---
> Linux/KVM has a similar patch :
>
> KVM: x86: Do not change ICR on write to APIC_SELF_IPI
> https://github.com/torvalds/linux/commit/d22a81b304a27fca6124174a8e842e826c193466
>
>  xen/arch/x86/hvm/vlapic.c | 21 ++++++++++++++++-----
>  1 file changed, 16 insertions(+), 5 deletions(-)
>
> diff --git a/xen/arch/x86/hvm/vlapic.c b/xen/arch/x86/hvm/vlapic.c
> index 885f5d304b..bb105225e2 100644
> --- a/xen/arch/x86/hvm/vlapic.c
> +++ b/xen/arch/x86/hvm/vlapic.c
> @@ -963,6 +963,17 @@ static int cf_check vlapic_mmio_write(
>      return X86EMUL_OKAY;
>  }
>  
> +/*
> + * A write to the SELF IPI register sends a fixed, edge triggered IPI with
> + * the given vector to the local APIC itself.  Unlike an ICR write it doesn't
> + * update the ICR, which is guest visible, in x2APIC mode even without any
> + * intervention by Xen when APIC-register virtualization is in use.
> + */
> +static void vlapic_self_ipi(struct vlapic *vlapic, uint32_t val)
> +{
> +    vlapic_ipi(vlapic, APIC_DEST_SELF | (val & APIC_VECTOR_MASK), 0);
> +}

I'm not sure a wrapper is really worth it, but if you do care to
continue with the patch, then you want a uint8_t vec here, and drop the
mask.

~Andrew