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[PATCH] drivers/char: Add several newer PCI IDs for Intel LPSS

From: Marek Marczykowski-Górecki <marmarek@xxxxxxxxxxxxxxxxxxxxxx>

Date: Tue, 13 Oct 2026 21:07:31 +0200

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Cc: Marek Marczykowski-Górecki <marmarek@xxxxxxxxxxxxxxxxxxxxxx>, Andrew Cooper <andrew.cooper3@xxxxxxxxxx>, Anthony PERARD <anthony.perard@xxxxxxxxxx>, Michal Orzel <michal.orzel@xxxxxxx>, Jan Beulich <jbeulich@xxxxxxxx>, Julien Grall <julien@xxxxxxx>, Roger Pau Monné <roger@xxxxxxxxxxxxxx>, Stefano Stabellini <sstabellini@xxxxxxxxxx>

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Include PCI IDs of UART ports on Intel RPL - PTL. Based on Linux driver and hwdata, they all share the same parameters. Signed-off-by: Marek Marczykowski-Górecki <marmarek@xxxxxxxxxxxxxxxxxxxxxx> --- I tested it on MTL, but given Linux driver handles them uniformly, I assume others work too. The list gets quite long, would it be preferred to have a macro to reduce (at least similar) entries to one-liners? In Linux driver it looks this way: /* MTL-P */ { PCI_VDEVICE(INTEL, 0x7e25), .driver_data = (kernel_ulong_t)&bxt_uart_info }, { PCI_VDEVICE(INTEL, 0x7e26), .driver_data = (kernel_ulong_t)&bxt_uart_info }, ... --- xen/drivers/char/ns16550.c | 132 +++++++++++++++++++++++++++++++++++++ 1 file changed, 132 insertions(+) diff --git a/xen/drivers/char/ns16550.c b/xen/drivers/char/ns16550.c index cdda28879e66..be388c8e6582 100644 --- a/xen/drivers/char/ns16550.c +++ b/xen/drivers/char/ns16550.c @@ -1245,6 +1245,138 @@ static const struct ns16550_config __initconst uart_config[] = .dev_id = 0x7adc, .param = param_intel_lpss }, + /* Intel Corp. RPL-S LPSS PCI UART #0 */ + { + .vendor_id = PCI_VENDOR_ID_INTEL, + .dev_id = 0x7a28, + .param = param_intel_lpss + }, + /* Intel Corp. RPL-S LPSS PCI UART #1 */ + { + .vendor_id = PCI_VENDOR_ID_INTEL, + .dev_id = 0x7a29, + .param = param_intel_lpss + }, + /* Intel Corp. RPL-S LPSS PCI UART #2 */ + { + .vendor_id = PCI_VENDOR_ID_INTEL, + .dev_id = 0x7a5c, + .param = param_intel_lpss + }, + /* Intel Corp. LNL-M LPSS PCI UART #0 */ + { + .vendor_id = PCI_VENDOR_ID_INTEL, + .dev_id = 0xa825, + .param = param_intel_lpss + }, + /* Intel Corp. LNL-M LPSS PCI UART #1 */ + { + .vendor_id = PCI_VENDOR_ID_INTEL, + .dev_id = 0xa826, + .param = param_intel_lpss + }, + /* Intel Corp. LNL-M LPSS PCI UART #2 */ + { + .vendor_id = PCI_VENDOR_ID_INTEL, + .dev_id = 0xa852, + .param = param_intel_lpss + }, + /* Intel Corp. MTL-P LPSS PCI UART #0 */ + { + .vendor_id = PCI_VENDOR_ID_INTEL, + .dev_id = 0x7e25, + .param = param_intel_lpss + }, + /* Intel Corp. MTL-P LPSS PCI UART #1 */ + { + .vendor_id = PCI_VENDOR_ID_INTEL, + .dev_id = 0x7e26, + .param = param_intel_lpss + }, + /* Intel Corp. MTL-P LPSS PCI UART #2 */ + { + .vendor_id = PCI_VENDOR_ID_INTEL, + .dev_id = 0x7e52, + .param = param_intel_lpss + }, + /* Intel Corp. MTP-S LPSS PCI UART #0 */ + { + .vendor_id = PCI_VENDOR_ID_INTEL, + .dev_id = 0x7f28, + .param = param_intel_lpss + }, + /* Intel Corp. MTP-S LPSS PCI UART #1 */ + { + .vendor_id = PCI_VENDOR_ID_INTEL, + .dev_id = 0x7f29, + .param = param_intel_lpss + }, + /* Intel Corp. MTP-S LPSS PCI UART #2 */ + { + .vendor_id = PCI_VENDOR_ID_INTEL, + .dev_id = 0x7f5c, + .param = param_intel_lpss + }, + /* Intel Corp. MTP-S LPSS PCI UART #3 */ + { + .vendor_id = PCI_VENDOR_ID_INTEL, + .dev_id = 0x7f5d, + .param = param_intel_lpss + }, + /* Intel Corp. NVL-H LPSS PCI UART #0 */ + { + .vendor_id = PCI_VENDOR_ID_INTEL, + .dev_id = 0xd325, + .param = param_intel_lpss + }, + /* Intel Corp. NVL-H LPSS PCI UART #1 */ + { + .vendor_id = PCI_VENDOR_ID_INTEL, + .dev_id = 0xd326, + .param = param_intel_lpss + }, + /* Intel Corp. NVL-H LPSS PCI UART #2 */ + { + .vendor_id = PCI_VENDOR_ID_INTEL, + .dev_id = 0xd352, + .param = param_intel_lpss + }, + /* Intel Corp. PTL-H LPSS PCI UART #0 */ + { + .vendor_id = PCI_VENDOR_ID_INTEL, + .dev_id = 0xe325, + .param = param_intel_lpss + }, + /* Intel Corp. PTL-H LPSS PCI UART #1 */ + { + .vendor_id = PCI_VENDOR_ID_INTEL, + .dev_id = 0xe326, + .param = param_intel_lpss + }, + /* Intel Corp. PTL-H LPSS PCI UART #2 */ + { + .vendor_id = PCI_VENDOR_ID_INTEL, + .dev_id = 0xe352, + .param = param_intel_lpss + }, + /* Intel Corp. PTL-P LPSS PCI UART #0 */ + { + .vendor_id = PCI_VENDOR_ID_INTEL, + .dev_id = 0xe425, + .param = param_intel_lpss + }, + /* Intel Corp. PTL-P LPSS PCI UART #1 */ + { + .vendor_id = PCI_VENDOR_ID_INTEL, + .dev_id = 0xe426, + .param = param_intel_lpss + }, + /* Intel Corp. PTL-P LPSS PCI UART #2 */ + { + .vendor_id = PCI_VENDOR_ID_INTEL, + .dev_id = 0xe452, + .param = param_intel_lpss + }, /* WCH CH382 2S1P */ { .vendor_id = PCI_VENDOR_ID_WCHIC, -- 2.54.0

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