[PATCH v3 16/39] xen/riscv: decouple INSN_PSEUDO_VS_* from the hypervisor's XLEN

[Oleksii Kurochko <oleksii.kurochko@xxxxxxxxx>]

htinst reports a pseudoinstruction when a guest page fault is taken on an
implicit memory access done for VS-stage address translation. Four such
values are defined, differing in the access type (read or write) and in the
access width: 4 bytes (0x2000/0x2020) or 8 bytes (0x3000/0x3020).

That width is the width of a VS-stage PTE, i.e. it follows the guest's
paging mode (4 bytes for Sv32, 8 bytes for Sv39 and wider) and has nothing
to do with the XLEN Xen itself is built for. Yet only one pair is defined,
selected by Xen's XLEN and named as if it were the only one, so the 4-byte
forms, which a guest running with VSXL=32 and Sv32 in vsatp produces, can't
be named at all on RV64.

Define all four values unconditionally instead, named after the access width
they encode rather than after the build's XLEN.

Dropping the ladder loses no build-time coverage: a build for an XLEN other
than 32 or 64 already fails on the equivalent ladders in asm/asm.h and
asm/config.h, so no replacement #error is needed here. Adding one keyed on
CONFIG_RISCV_* would in any case re-introduce exactly the conflation this
patch removes.

This diverges from the imported version of riscv_encoding.h.

No functional change: the values have no user.

Signed-off-by: Oleksii Kurochko <oleksii.kurochko@xxxxxxxxx>
---
Changes in v3:
 - Update the commit message: the values no longer have a user in this
   series, as htinst_is_pseudo() recognizes a pseudoinstruction by its
   bits[1:0].
 - Use VSXLEN=32/64 instead of RV32/64 in the comments of the
   corresponding definitions.
---
Changes in v2:
 - New patch.
---
---
 xen/arch/riscv/include/asm/riscv_encoding.h | 24 +++++++--------------
 1 file changed, 8 insertions(+), 16 deletions(-)

diff --git a/xen/arch/riscv/include/asm/riscv_encoding.h 
b/xen/arch/riscv/include/asm/riscv_encoding.h
index 599ae3cd601a..2dbfd4d16067 100644
--- a/xen/arch/riscv/include/asm/riscv_encoding.h
+++ b/xen/arch/riscv/include/asm/riscv_encoding.h
@@ -837,25 +837,17 @@
 #define INSN_MASK_FENCE_TSO            0xffffffff
 #define INSN_MATCH_FENCE_TSO           0x8330000f
 
-#if __riscv_xlen == 64
-
-/* 64-bit read for VS-stage address translation (RV64) */
-#define INSN_PSEUDO_VS_LOAD            0x00003000
-
-/* 64-bit write for VS-stage address translation (RV64) */
-#define INSN_PSEUDO_VS_STORE   0x00003020
+/* 64-bit read for VS-stage address translation (VSXLEN=64) */
+#define INSN_PSEUDO_VS_LOAD64          0x00003000
 
-#elif __riscv_xlen == 32
+/* 64-bit write for VS-stage address translation (VSXLEN=64) */
+#define INSN_PSEUDO_VS_STORE64         0x00003020
 
-/* 32-bit read for VS-stage address translation (RV32) */
-#define INSN_PSEUDO_VS_LOAD            0x00002000
+/* 32-bit read for VS-stage address translation (VSXLEN=32) */
+#define INSN_PSEUDO_VS_LOAD32          0x00002000
 
-/* 32-bit write for VS-stage address translation (RV32) */
-#define INSN_PSEUDO_VS_STORE   0x00002020
-
-#else
-#error "Unexpected __riscv_xlen"
-#endif
+/* 32-bit write for VS-stage address translation (VSXLEN=32) */
+#define INSN_PSEUDO_VS_STORE32         0x00002020
 
 #define INSN_IS_16BIT(insn)    (((insn) & 3) != 3)
 #define INSN_IS_32BIT(insn)    (!INSN_IS_16BIT(insn) && ((insn) & 0x1c) != 
0x1c)
-- 
2.55.0