[PATCH v3 0/6] xen/riscv: fix boot on missing extensions and MMU setup bugs

[Baptiste Le Duc <baptiste.le-duc@xxxxxxxxxx>]

This series introduces bugs fixes that were found while bringing up CI
support for the HiFive Premier P550 board with a basic smoke test. The
board-support series itself will follow separately as it depends on
PLIC/vPLIC and dom0less support that have not been upstreamed yet. This
series carries only the independent fixes found along the way, none of them
need the board-support series to apply.

This series:
    1: Docs: sync required ISA extensions with required_extensions[]
    2: Rename PTE "permissions" to "pte_flags"
    3: Fix A/D bit handling in G-stage mappings
    4: Fix A/D bit handling in Xen's page-table mappings
    5: Use pte_is_valid() in pte_is_mapping()
    6: Make Zihintpause no longer a required extension

CI pipeline:
https://gitlab.com/xen-project/people/baptleduc/xen/-/pipelines/2894144143

---
Changes since v2:
- Drop v2 patches 5 and 6, already committed:
    d8ca89f26c8a ("xen/riscv: flush speculatively cached Bare-mode TLB entries 
in turn_on_mmu()")
    08a898b93d21 ("xen/riscv: fix level_map_mask truncation on load_start")
- Drop "xen/riscv: make Svpbmt no longer a required extension".
  It relaxed Svpbmt so boards without it, like the HiFive P550, could boot.
  But without Svpbmt, DMA-noncoherent devices do not snoop the CPU caches
  and can read stale data from DRAM. Mainline Linux has the same problem,
  which is explained and reproducible in [1]. Fixing it needs a lot of
  machinery we do not need yet, and Svpbmt is mandatory in RVA23, so
  keeping it required is simpler and safer. An RFC will follow with a fix
  inspired by [2].
- Add three new patches:
    docs/riscv: sync required ISA extensions with required_extensions[]
    xen/riscv: rename PTE "permissions" to "pte_flags"
    xen/riscv: use pte_is_valid() in pte_is_mapping()
- Address review comments.

[1] https://github.com/davidlohr/vanilla-kernel-sifive-p550/tree/master
[2] https://lwn.net/Articles/996819/
---
Changes since v1:
- address ML comments
- rename some patchs
- add new patch-fix: 242dd1f890e4 ("xen/riscv: fix level_map_mask
  truncation on load_start") discovered when working on Spacemit K3 support

To: xen-devel@xxxxxxxxxxxxxxxxxxxx
Cc: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
Cc: Anthony PERARD <anthony.perard@xxxxxxxxxx>
Cc: Michal Orzel <michal.orzel@xxxxxxx>
Cc: Jan Beulich <jbeulich@xxxxxxxx>
Cc: Julien Grall <julien@xxxxxxx>
Cc: Roger Pau Monné <roger@xxxxxxxxxxxxxx>
Cc: Stefano Stabellini <sstabellini@xxxxxxxxxx>
Cc: Alistair Francis <alistair.francis@xxxxxxx>
Cc: Connor Davis <connojdavis@xxxxxxxxx>
Cc: Oleksii Kurochko <oleksii.kurochko@xxxxxxxxx>
Cc: Zheng Zhang <Zheng Zhang <zhangzheng@xxxxxxxxxxx>

---
Baptiste Le Duc (5):
      xen/riscv: rename PTE "permissions" to "pte_flags"
      xen/riscv: fix A/D bit handling in G-stage mappings
      xen/riscv: fix A/D bits in Xen's page-table mappings
      xen/riscv: use pte_is_valid() in pte_is_mapping()
      xen/riscv: make Zihintpause no longer a required extension

Oleksii Kurochko (1):
      docs/riscv: sync required ISA extensions with required_extensions[]

 docs/misc/riscv/booting.txt             | 27 +++++++++++-----
 xen/arch/riscv/cpufeature.c             | 56 ++++++++++++++++++++++++++++++++-
 xen/arch/riscv/include/asm/cpufeature.h |  1 +
 xen/arch/riscv/include/asm/mm.h         |  5 +--
 xen/arch/riscv/include/asm/page.h       | 35 +++++++++++----------
 xen/arch/riscv/include/asm/sbi.h        |  8 +++++
 xen/arch/riscv/mm.c                     | 11 +++----
 xen/arch/riscv/p2m.c                    | 44 ++++++++------------------
 8 files changed, 123 insertions(+), 64 deletions(-)
---
base-commit: 4c1aba82cff95ab11f7fe4af8965a06703537288
change-id: 20260902-riscv-fix-boot-missing-ext-a79c23bad694

Best regards,
--  
Baptiste Le Duc <baptiste.le-duc@xxxxxxxxxx>