[PATCH v3 025/114] hw/riscv: gate boards with target_is_base_riscv

[Yonggang Luo <luoyonggang@xxxxxxxxx>]

- Set TypeInfo.is_available to target_is_base_riscv on RISC-V machines
  so a combined qemu-system lists them only for riscv32/riscv64.
---
 hw/riscv/k230.c            | 1 +
 hw/riscv/microchip_pfsoc.c | 1 +
 hw/riscv/opentitan.c       | 1 +
 hw/riscv/shakti_c.c        | 1 +
 hw/riscv/sifive_e.c        | 1 +
 hw/riscv/sifive_u.c        | 1 +
 hw/riscv/spike.c           | 1 +
 hw/riscv/tt_atlantis.c     | 1 +
 hw/riscv/virt.c            | 1 +
 hw/riscv/xiangshan_kmh.c   | 1 +
 10 files changed, 10 insertions(+)

diff --git a/hw/riscv/k230.c b/hw/riscv/k230.c
index 79715265da6..3890cb6357d 100644
--- a/hw/riscv/k230.c
+++ b/hw/riscv/k230.c
@@ -557,6 +557,7 @@ static void k230_machine_class_init(ObjectClass *oc, const 
void *data)
 static const TypeInfo k230_machine_typeinfo = {
     .name       = TYPE_RISCV_K230_MACHINE,
     .parent     = TYPE_MACHINE,
+    .is_available = target_is_base_riscv,
     .class_init = k230_machine_class_init,
     .instance_init = k230_machine_instance_init,
     .instance_size = sizeof(K230MachineState),
diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
index cc4b6bc3529..103c0d7f7ca 100644
--- a/hw/riscv/microchip_pfsoc.c
+++ b/hw/riscv/microchip_pfsoc.c
@@ -756,6 +756,7 @@ static void 
microchip_icicle_kit_machine_class_init(ObjectClass *oc,
 static const TypeInfo microchip_icicle_kit_machine_typeinfo = {
     .name       = MACHINE_TYPE_NAME("microchip-icicle-kit"),
     .parent     = TYPE_MACHINE,
+    .is_available = target_is_base_riscv,
     .class_init = microchip_icicle_kit_machine_class_init,
     .instance_init = microchip_icicle_kit_machine_instance_init,
     .instance_size = sizeof(MicrochipIcicleKitState),
diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
index 9e3db34eed9..db1fb3e3347 100644
--- a/hw/riscv/opentitan.c
+++ b/hw/riscv/opentitan.c
@@ -337,6 +337,7 @@ static const TypeInfo open_titan_types[] = {
     }, {
         .name           = TYPE_OPENTITAN_MACHINE,
         .parent         = TYPE_MACHINE,
+        .is_available   = target_is_base_riscv,
         .instance_size  = sizeof(OpenTitanState),
         .class_init     = opentitan_machine_class_init,
         .is_available   = target_is_riscv32,
diff --git a/hw/riscv/shakti_c.c b/hw/riscv/shakti_c.c
index 0f96258b764..e8ae770f7ca 100644
--- a/hw/riscv/shakti_c.c
+++ b/hw/riscv/shakti_c.c
@@ -95,6 +95,7 @@ static void shakti_c_machine_class_init(ObjectClass *klass, 
const void *data)
 static const TypeInfo shakti_c_machine_type_info = {
     .name = TYPE_RISCV_SHAKTI_MACHINE,
     .parent = TYPE_MACHINE,
+    .is_available = target_is_base_riscv,
     .class_init = shakti_c_machine_class_init,
     .instance_init = shakti_c_machine_instance_init,
     .instance_size = sizeof(ShaktiCMachineState),
diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
index 1b6f9ab4fee..087d0c48e1e 100644
--- a/hw/riscv/sifive_e.c
+++ b/hw/riscv/sifive_e.c
@@ -165,6 +165,7 @@ static void sifive_e_machine_class_init(ObjectClass *oc, 
const void *data)
 static const TypeInfo sifive_e_machine_typeinfo = {
     .name       = MACHINE_TYPE_NAME("sifive_e"),
     .parent     = TYPE_MACHINE,
+    .is_available = target_is_base_riscv,
     .class_init = sifive_e_machine_class_init,
     .instance_init = sifive_e_machine_instance_init,
     .instance_size = sizeof(SiFiveEState),
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 344f3d915d7..d5cc9255da6 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -679,6 +679,7 @@ static void sifive_u_machine_class_init(ObjectClass *oc, 
const void *data)
 static const TypeInfo sifive_u_machine_typeinfo = {
     .name       = MACHINE_TYPE_NAME("sifive_u"),
     .parent     = TYPE_MACHINE,
+    .is_available = target_is_base_riscv,
     .class_init = sifive_u_machine_class_init,
     .instance_init = sifive_u_machine_instance_init,
     .instance_size = sizeof(SiFiveUState),
diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
index 63cf77e1de3..4bb58ec6203 100644
--- a/hw/riscv/spike.c
+++ b/hw/riscv/spike.c
@@ -292,6 +292,7 @@ static void spike_machine_class_init(ObjectClass *oc, const 
void *data)
 static const TypeInfo spike_machine_typeinfo = {
     .name       = MACHINE_TYPE_NAME("spike"),
     .parent     = TYPE_MACHINE,
+    .is_available = target_is_base_riscv,
     .class_init = spike_machine_class_init,
     .instance_init = spike_machine_instance_init,
     .instance_size = sizeof(SpikeState),
diff --git a/hw/riscv/tt_atlantis.c b/hw/riscv/tt_atlantis.c
index 086e95bd2d1..6e7272d705c 100644
--- a/hw/riscv/tt_atlantis.c
+++ b/hw/riscv/tt_atlantis.c
@@ -699,6 +699,7 @@ static const TypeInfo tt_atlantis_types[] = {
     }, {
         .name       = MACHINE_TYPE_NAME("tt-atlantis"),
         .parent     = TYPE_MACHINE,
+        .is_available = target_is_base_riscv,
         .class_init = tt_atlantis_machine_class_init,
         .instance_size = sizeof(TTAtlantisState),
         .is_available = target_is_riscv64,
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 0edf75fefc3..2240a516d85 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -1202,6 +1202,7 @@ static void virt_machine_class_init(ObjectClass *oc, 
const void *data)
 static const TypeInfo virt_machine_typeinfo = {
     .name       = TYPE_RISCV_VIRT_MACHINE,
     .parent     = TYPE_MACHINE,
+    .is_available = target_is_base_riscv,
     .class_init = virt_machine_class_init,
     .instance_init = virt_machine_instance_init,
     .instance_finalize = virt_machine_instance_finalize,
diff --git a/hw/riscv/xiangshan_kmh.c b/hw/riscv/xiangshan_kmh.c
index 6bc669421fe..9578a11aee6 100644
--- a/hw/riscv/xiangshan_kmh.c
+++ b/hw/riscv/xiangshan_kmh.c
@@ -220,6 +220,7 @@ static void xiangshan_kmh_machine_class_init(ObjectClass 
*klass, const void *dat
 static const TypeInfo xiangshan_kmh_machine_info = {
     .name = TYPE_XIANGSHAN_KMH_MACHINE,
     .parent = TYPE_MACHINE,
+    .is_available = target_is_base_riscv,
     .instance_size = sizeof(XiangshanKmhState),
     .class_init = xiangshan_kmh_machine_class_init,
     .is_available = target_is_riscv64,
-- 
2.52.0.windows.1