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[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] Re: [PATCH v2 2/6] xen/riscv: set A/D bits in Xen's page-table mappings under Svade
# Add your code comments below. There is no need to trim or delete # any existing content -- just insert your comments under the relevant # lines of code. Lines starting with "> " are quoted diff context and # lines starting with "| " are comments from other reviewers. # The final email will be reformatted automatically to include only # the sections that have your comments. # > The previous patch set A/D bits in case of the Svade extension for G-stage > mappings. Xen's own S-stage mappings need the same fix as both > setup_initial_mapping() (the boot page tables) and arch_pmap_map() (the > fixmap) build leaf PTEs directly instead of going through > pt_update_entry(), which is what adds A/D bits. So with Svade, both would > fault on first access. > > Add PTE_ACCESSED to all PAGE_HYPERVISOR_* and also PTE_DIRTY to > PAGE_HYPERVISOR_RW as it needs to be set during a write to avoid a fault. > This fixes arch_pmap_map() for free, since it already builds its PTE from > PAGE_HYPERVISOR_RW. Switch setup_initial_mapping() to use these macros for > its default, text and rodata permissions, and for the temporary root entry > built by check_pgtbl_mode_support(), instead of the equivalent raw bit > lists. The latter drops PTE_WRITABLE, going from RWX to RX, but this is > harmless, as that entry only has to make the current instruction stream > fetchable between the two CSR_SATP writes used to probe SATP mode support, > and nothing writes through it. > > Drop the now-redundant PTE_LEAF_DEFAULT, since converting the last > open-coded site above leaves it with no user outside page.h itself. > > A PTE is a table entry iff PTE_VALID is set and R/W/X are all clear, so > update pte_is_table() and pte_is_mapping() accordingly. > > Assisted-by: Claude:claude-opus-5 > Signed-off-by: Baptiste Le Duc <baptiste.le-duc@xxxxxxxxxx> Tested-by: Zheng Zhang <zhangzheng@xxxxxxxxxxx> -- Zhang Zheng <zhangzheng@xxxxxxxxxxx>
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