[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [PATCH v3 4/4] xen/arm: handle irq_set_type() failures
- To: Mykola Kvach <mykola_kvach@xxxxxxxx>, <xen-devel@xxxxxxxxxxxxxxxxxxxx>
- From: "Orzel, Michal" <michal.orzel@xxxxxxx>
- Date: Tue, 15 Sep 2026 12:05:20 +0200
- Arc-authentication-results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=epam.com smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none (0)
- Arc-message-signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=j006rmxLo+ApI4QfmDcFsOzeYmInP1NFjds5PKVI7+U=; b=VM++YpADTiu6HwmSnYGMftVcc5cKUp/e+/Lhx78FzzCY1QwsltHyG78MlSJ6C2HF4wigLxbDLcfvWqo55Q5KlXQWInYwH56XoI3YwFpCJ6wQeTvcIWR+YyBu/wdBVOxsXcNmLavoECRzBm2Pj+N3KAb+f13n65he/JW1GQ/FrojJnfr5lAchdPJSgKYdfwUo7QeNYI50OmflcCq8AuJtxWKKbIDkHyTWGprzJIpwP9cncyRYzGpR2dDHhUbX9wd7VnLMi/KCOidpvLkE2ZwlHba6HIyDDe+1U5UJMxXOLhZlYLiDOUEzDQ62K2pzgcjflV6KJEUdBIrBkTSm3UZ36Q==
- Arc-seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=DnRt4yTDNKzemUtdIFmlFjFGommpMs7KyLPRcWLiQR8fT9cXW3dxgr/9kGJd+zNmJSZ6u4z0n/KsiW2YrjMdCW+oMLQ+LeAh7uOWtdOBGEgxjaveoWcx8oB98yi2KRlgLqKMEMZUOTwNsfjawwUUhs9uH5leMWeycQOyLj51QhmVCCMnKd3+RrDl1U9phW1vm+TUUfYgl2rsQnGlF1ofGKB4JgNWvWl/YWgUhG2bH+VSSERu1JrjKEcBmb/fl6mejNTp3Al6rhAJV9bepIIM9eAexWijYkcEwRTNP7u2u1HeQM4MZfVZ0KcIbzmJScA3mAaOOdabvvQxsimm7Natjg==
- Authentication-results: eu.smtp.expurgate.cloud; dkim=pass header.s=selector1 header.d=amd.com header.i="@amd.com" header.h="From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck"
- Cc: Stefano Stabellini <sstabellini@xxxxxxxxxx>, Julien Grall <julien@xxxxxxx>, Bertrand Marquis <bertrand.marquis@xxxxxxx>, "Volodymyr Babchuk" <Volodymyr_Babchuk@xxxxxxxx>, Andrew Cooper <andrew.cooper3@xxxxxxxxxx>, Anthony PERARD <anthony.perard@xxxxxxxxxx>, "Jan Beulich" <jbeulich@xxxxxxxx>, Roger Pau Monné <roger@xxxxxxxxxxxxxx>, Jens Wiklander <jenswi@xxxxxxxxxx>
- Delivery-date: Tue, 15 Sep 2026 10:05:38 +0000
- List-id: Xen developer discussion <xen-devel.lists.xenproject.org>
On 18-Aug-26 13:33, Mykola Kvach wrote:
> Several Arm firmware initialization paths discard irq_set_type()'s return
> value, violating MISRA C Rule 17.7. If trigger configuration fails,
> initialization continues with an IRQ that was not configured as requested.
>
> GTDT and MADT retain rejected timer and maintenance INTIDs.
> check_timer_irq_cfg() and release_irq() later perform unconditional
> descriptor lookups on those values. Xen has no backing descriptors for
> INTIDs 1024 through 4095, so retaining one can cause an out-of-bounds
> access.
>
> Check the return value in the GTDT, MADT, SPCR, and FF-A paths. Store timer
> INTIDs only after successful trigger configuration, make GTDT parsing
> failure fatal, and stop UART or notification setup when trigger
> configuration fails.
>
> Signed-off-by: Mykola Kvach <mykola_kvach@xxxxxxxx>
This should be the first patch in a series that can be committed right away.
Reviewed-by: Michal Orzel <michal.orzel@xxxxxxx>
~Michal
|