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[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] Re: [PATCH v2 20/39] xen/riscv: detect Shtvala
On 9/7/26 5:57 PM, Baptiste Le Duc wrote: Shtvala says that htval is written with the faulting guest physical address on a guest-page fault. The H extension itself allows an implementation to write htval with either that address or with zero, so where the extension is absent a zero htval cannot be told apart from a genuine fault on guest physical address 0-3. It is not offered to guests. Shtvala describes the HS-mode trap interface, which a VS-mode guest never sees, and the H extension it belongs to is already withheld from guests. Its guest-facing counterpart is a separate extension, Shvstvala. Signed-off-by: Oleksii Kurochko <oleksii.kurochko@xxxxxxxxx>I thought this commit message is not very clear. Here is a more direct suggestion: ``` The H extension allows htval, on a guest-page fault, to be written with either the faulting guest physical address or zero. Shtvala extension removes the ambiguity of this zero-write by guaranteeing that htval is written with the faulting guest physical address in every circumstance permitted by the ISA. Not offered to guests: Shtvala describes htval, an HS-mode-only trap register a VS-mode guest never touches and the H extension it belongs to is already hidden from guests. The guest-visible equivalent is a separate extension, Shvstvala, covering vstval instead. ``` Sounds good to me. I will apply your suggestion. Btw, I saw Linux has Documentation/devicetree/bindings/riscv/extensions.yaml which describes all of the extensions supported, don't you think it would be useful to have the same in docs/misc/devicetree/...? I think it could be useful.I think also about booting.txt already exitsted in the codebase. Would you be okay with that? I think I will add the section to booting.txt and pointing to riscv_isa_ext[] in cpufeature.c and so we won't miss an update of doc if we will add or remove support of an extension. Does it sound good to you? ~ Oleksii
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