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Re: [PATCH v2 16/39] xen/riscv: extend exception tables with type and data fields



On 2026-09-08 08:06:29+02:00, Jan Beulich wrote:
> On 07.09.2026 17:57, Baptiste Le Duc wrote:
> 
> >> --- a/xen/arch/riscv/include/asm/processor.h
> > Comment claims ->zero "must always read as 0" as it's hard-wired to zero
> > by the HW, but nothing enforces that, it's still a plain writable
> > unsigned long. Maybe a write-side counterpart that special-cases num==0
> > as a no-op, or with a minimum ASSERT(num != 0) / BUG_ON(num == 0) to
> > anticipate any future forbidden writes.
> 
> With polarity inverted, though.
Yes sorry, it should be ASSERT(num == 0) / BUG_ON(num != 0)
> 
> Jan





 


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