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[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] [PATCH 1/2] ARM: fix typos in comments
Fix typos in comments, reported by scripts/checkpatch.pl using the
misspelling list in scripts/spelling.txt. Only touches comments, no code
changes.
Assisted-by: Cursor:claude-opus-5
Signed-off-by: Hemanth Selam <hemanth.selam@xxxxxxxxx>
---
arch/arm/boot/compressed/head.S | 2 +-
arch/arm/include/asm/uaccess.h | 2 +-
arch/arm/kernel/cpuidle.c | 2 +-
arch/arm/mm/cache-l2x0.c | 2 +-
arch/arm/mm/context.c | 4 ++--
arch/arm/probes/decode.h | 2 +-
arch/arm/probes/kprobes/opt-arm.c | 4 ++--
arch/arm/probes/kprobes/test-core.c | 2 +-
arch/arm/xen/hypercall.S | 4 ++--
9 files changed, 12 insertions(+), 12 deletions(-)
diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
index 9f406e9c0ea6..e117f2b4dea9 100644
--- a/arch/arm/boot/compressed/head.S
+++ b/arch/arm/boot/compressed/head.S
@@ -955,7 +955,7 @@ call_cache_fn: adr r12, proc_types
/*
* On v7-M the processor id is located in the V7M_SCB_CPUID
* register, but as cache handling is IMPLEMENTATION DEFINED on
- * v7-M (if existant at all) we just return early here.
+ * v7-M (if existent at all) we just return early here.
* If V7M_SCB_CPUID were used the cpu ID functions (i.e.
* __armv7_mmu_cache_{on,off,flush}) would be selected which
* use cp15 registers that are not implemented on v7-M.
diff --git a/arch/arm/include/asm/uaccess.h b/arch/arm/include/asm/uaccess.h
index 1593cf3b9800..9805001f9d72 100644
--- a/arch/arm/include/asm/uaccess.h
+++ b/arch/arm/include/asm/uaccess.h
@@ -24,7 +24,7 @@
* These two functions allow hooking accesses to userspace to increase
* system integrity by ensuring that the kernel can not inadvertantly
* perform such accesses (eg, via list poison values) which could then
- * be exploited for priviledge escalation.
+ * be exploited for privilege escalation.
*/
#if defined(CONFIG_CPU_SW_DOMAIN_PAN)
diff --git a/arch/arm/kernel/cpuidle.c b/arch/arm/kernel/cpuidle.c
index fba1f8bb03b5..784457ac7b2b 100644
--- a/arch/arm/kernel/cpuidle.c
+++ b/arch/arm/kernel/cpuidle.c
@@ -79,7 +79,7 @@ static const struct cpuidle_ops *__init
arm_cpuidle_get_ops(const char *method)
* cpuidle_ops are tagged __initconst and will be unloaded after the init
* process.
*
- * Return 0 on sucess, -ENOENT if no 'enable-method' is defined, -EOPNOTSUPP if
+ * Return 0 on success, -ENOENT if no 'enable-method' is defined, -EOPNOTSUPP
if
* no cpuidle_ops is registered for the 'enable-method', or if either init or
* suspend callback isn't defined.
*/
diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index 470867160076..0eaaf99d3d11 100644
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -1381,7 +1381,7 @@ static void aurora_pa_range(unsigned long start, unsigned
long end,
unsigned long flags;
/*
- * round start and end adresses up to cache line size
+ * round start and end addresses up to cache line size
*/
start &= ~(CACHE_LINE_SIZE - 1);
end = ALIGN(end, CACHE_LINE_SIZE);
diff --git a/arch/arm/mm/context.c b/arch/arm/mm/context.c
index 4204ffa2d104..95d477cab0f5 100644
--- a/arch/arm/mm/context.c
+++ b/arch/arm/mm/context.c
@@ -76,7 +76,7 @@ void a15_erratum_get_cpumask(int this_cpu, struct mm_struct
*mm,
#ifdef CONFIG_ARM_LPAE
/*
- * With LPAE, the ASID and page tables are updated atomicly, so there is
+ * With LPAE, the ASID and page tables are updated atomically, so there is
* no need for a reserved set of tables (the active ASID tracking prevents
* any issues across a rollover).
*/
@@ -243,7 +243,7 @@ void check_and_switch_context(struct mm_struct *mm, struct
task_struct *tsk)
check_vmalloc_seq(mm);
/*
- * We cannot update the pgd and the ASID atomicly with classic
+ * We cannot update the pgd and the ASID atomically with classic
* MMU, so switch exclusively to global mappings to avoid
* speculative page table walking with the wrong TTBR.
*/
diff --git a/arch/arm/probes/decode.h b/arch/arm/probes/decode.h
index facc889d05ee..b09c44ba1030 100644
--- a/arch/arm/probes/decode.h
+++ b/arch/arm/probes/decode.h
@@ -250,7 +250,7 @@ enum decode_reg_type {
REG_TYPE_NOPCWB, /* No PC if load/store write-back flag also set */
/* The following types are used when the encoding for PC indicates
- * another instruction form. This distiction only matters for test
+ * another instruction form. This distinction only matters for test
* case coverage checks.
*/
REG_TYPE_NOPCX, /* Register must not be PC */
diff --git a/arch/arm/probes/kprobes/opt-arm.c
b/arch/arm/probes/kprobes/opt-arm.c
index 966c6042c5ad..a3aed8c01c98 100644
--- a/arch/arm/probes/kprobes/opt-arm.c
+++ b/arch/arm/probes/kprobes/opt-arm.c
@@ -210,11 +210,11 @@ int arch_prepare_optimized_kprobe(struct optimized_kprobe
*op, struct kprobe *or
*
* So the maximum forward branch should be:
* (0x007fffff << 2) = 0x01fffffc = 0x1fffffc
- * The maximum backword branch should be:
+ * The maximum backward branch should be:
* (0xff800000 << 2) = 0xfe000000 = -0x2000000
*
* We can simply check (rel & 0xfe000003):
- * if rel is positive, (rel & 0xfe000000) shoule be 0
+ * if rel is positive, (rel & 0xfe000000) should be 0
* if rel is negitive, (rel & 0xfe000000) should be 0xfe000000
* the last '3' is used for alignment checking.
*/
diff --git a/arch/arm/probes/kprobes/test-core.c
b/arch/arm/probes/kprobes/test-core.c
index 2de28088dac8..531fec3621b8 100644
--- a/arch/arm/probes/kprobes/test-core.c
+++ b/arch/arm/probes/kprobes/test-core.c
@@ -125,7 +125,7 @@
* .byte ARG_TYPE_END
* .byte TEST_ISA @ flags, including ISA being tested
* .short 50f-0f @ offset of 'test_before'
- * .short 2f-0f @ offset of 'test_after2' (if relevent)
+ * .short 2f-0f @ offset of 'test_after2' (if relevant)
* .short 99f-0f @ offset of 'test_done'
* @ start of test case code...
* 0:
diff --git a/arch/arm/xen/hypercall.S b/arch/arm/xen/hypercall.S
index f794dac9859a..b8b6192e310e 100644
--- a/arch/arm/xen/hypercall.S
+++ b/arch/arm/xen/hypercall.S
@@ -32,9 +32,9 @@
/*
* The Xen hypercall calling convention is very similar to the ARM
- * procedure calling convention: the first paramter is passed in r0, the
+ * procedure calling convention: the first parameter is passed in r0, the
* second in r1, the third in r2 and the fourth in r3. Considering that
- * Xen hypercalls have 5 arguments at most, the fifth paramter is passed
+ * Xen hypercalls have 5 arguments at most, the fifth parameter is passed
* in r4, differently from the procedure calling convention of using the
* stack for that case.
*
--
2.48.1
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