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[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] [PATCH v2 03/39] xen/riscv: set the guest's XLEN explicitly in hstatus.VSXL
hstatus.VSXL is WARL, so its reset value is implementation-defined. Xen
supports 64-bit guests only, so program it explicitly instead of relying
on whatever the hardware happens to leave there.
This matters beyond the guest's own view of itself: decoding a trapped
instruction depends on the effective XLEN of the guest, as the encodings
which exist for XLEN=64 only must not be recognized for a 32-bit one.
Signed-off-by: Oleksii Kurochko <oleksii.kurochko@xxxxxxxxx>
---
Changes in v2:
- new patch
---
---
xen/arch/riscv/domain.c | 8 +++++++-
xen/arch/riscv/include/asm/riscv_encoding.h | 2 ++
2 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/xen/arch/riscv/domain.c b/xen/arch/riscv/domain.c
index d94652809e36..57c37cb2dfc2 100644
--- a/xen/arch/riscv/domain.c
+++ b/xen/arch/riscv/domain.c
@@ -88,7 +88,13 @@ static void vcpu_csr_init(struct vcpu *v)
{
v->arch.hedeleg = HEDELEG_DEFAULT & csr_masks.hedeleg;
- vcpu_guest_cpu_user_regs(v)->hstatus = HSTATUS_SPV | HSTATUS_SPVP;
+ /*
+ * Xen supports 64-bit guests only, so set the guest's XLEN explicitly
+ * rather than leaving it to the WARL behaviour of hstatus.VSXL, which the
+ * decoding of a trapped instruction depends on.
+ */
+ vcpu_guest_cpu_user_regs(v)->hstatus =
+ HSTATUS_SPV | HSTATUS_SPVP | MASK_INSR(HSTATUS_VSXL_64, HSTATUS_VSXL);
v->arch.hideleg = HIDELEG_DEFAULT & csr_masks.hideleg;
diff --git a/xen/arch/riscv/include/asm/riscv_encoding.h
b/xen/arch/riscv/include/asm/riscv_encoding.h
index 03e186bcdb8c..c63e5e304691 100644
--- a/xen/arch/riscv/include/asm/riscv_encoding.h
+++ b/xen/arch/riscv/include/asm/riscv_encoding.h
@@ -68,6 +68,8 @@
#if __riscv_xlen == 64
#define HSTATUS_VSXL _UL(0x300000000)
#define HSTATUS_VSXL_SHIFT 32
+#define HSTATUS_VSXL_64 _UL(2)
+#define HSTATUS_VSXL_32 _UL(1)
#endif
#define HSTATUS_VTSR _UL(0x00400000)
#define HSTATUS_VTW _UL(0x00200000)
--
2.55.0
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