[PATCH v2] public/xen.h: Update comment on mmu_update sub-command size and PTE alignment

[Teddy Astie <teddy.astie@xxxxxxxxxx>]

HYPERVISOR_mmu_update passes a set of request, where each request has a pointer
to the PTE along with a sub-command.

The PTE alignment padding is used to transport the sub-command while the rest
is used as an address to a PTE entry. The current documentation state that the
2 first bits are used for sub-command, hence the other ones for PTE which
imply here a 4-bytes alignment on PTEs.

On PV64 and PV32-PAE guests, all pagetable PTEs are 8-bytes aligned, hence
off-by-4 PTEs addresses are always incorrect. Non-PAE PV32 guests used
"legacy pagetables" which had 4-byte aligned PTEs. However, support had
been completely removed since Xen 4.0, and was only available when Xen was
built in 32-bits non-PAE mode [1].

Current Xen logic behaves as if 3 bits are used as sub-command, thus all
off-by-4 PTEs are actually rejected as being unknown sub-commands.

Adjust the documentation to match the current logic implemented in Xen,
also expanding the documented sub-command parameter to 3 bits.

[1] 84d54d5d8b31 ("i386: Remove non-PAE hypervisor build target.")

Signed-off-by: Frediano Ziglio <frediano.ziglio@xxxxxxxxxx>
Signed-off-by: Teddy Astie <teddy.astie@xxxxxxxxxx>
---
v2:
* Fixed typos
* Added Frediano Ziglio S-o-B
* Added historical note regarding non-PAE Xen.

 xen/include/public/xen.h | 19 ++++++++++++-------
 1 file changed, 12 insertions(+), 7 deletions(-)

diff --git a/xen/include/public/xen.h b/xen/include/public/xen.h
index 2149b8dd38..cf32e74f14 100644
--- a/xen/include/public/xen.h
+++ b/xen/include/public/xen.h
@@ -218,16 +218,16 @@ DEFINE_XEN_GUEST_HANDLE(xen_ulong_t);
  *                     x == 0 => PFD == DOMID_SELF
  *                     x != 0 => PFD == x - 1
  *
- * Sub-commands: ptr[1:0] specifies the appropriate MMU_* command.
+ * Sub-commands: ptr[2:0] specifies the appropriate MMU_* command.
  * -------------
- * ptr[1:0] == MMU_NORMAL_PT_UPDATE:
+ * ptr[2:0] == MMU_NORMAL_PT_UPDATE:
  * Updates an entry in a page table belonging to PFD. If updating an L1 table,
  * and the new table entry is valid/present, the mapped frame must belong to
  * FD. If attempting to map an I/O page then the caller assumes the privilege
  * of the FD.
  * FD == DOMID_IO: Permit /only/ I/O mappings, at the priv level of the caller.
  * FD == DOMID_XEN: Map restricted areas of Xen's heap space.
- * ptr[:2]  -- Machine address of the page-table entry to modify.
+ * ptr[:3]  -- Machine address of the page-table entry to modify.
  * val      -- Value to write.
  *
  * There also certain implicit requirements when using this hypercall. The
@@ -260,21 +260,26 @@ DEFINE_XEN_GUEST_HANDLE(xen_ulong_t);
  * hypercall. Also if so desired the OS can also try to write to the PTE
  * and be trapped by the hypervisor (as the PTE entry is RO).
  *
+ * Note: Historically, Xen had support for non-PAE PV guests with 4-bytes wide
+ *       PTEs (if Xen was built in non-PAE mode); which support got removed in
+ *       Xen 4.0. As a result, in current Xen,, all PTE are now always 8-byte
+ *       aligned which allows expanding sub-commands part (now 3-bits wide).
+ *
  * To deallocate the pages, the operations are the reverse of the steps
  * mentioned above. The argument is MMUEXT_UNPIN_TABLE for all levels and the
  * pagetable MUST not be in use (meaning that the cr3 is not set to it).
  *
- * ptr[1:0] == MMU_MACHPHYS_UPDATE:
+ * ptr[2:0] == MMU_MACHPHYS_UPDATE:
  * Updates an entry in the machine->pseudo-physical mapping table.
- * ptr[:2]  -- Machine address within the frame whose mapping to modify.
+ * ptr[:3]  -- Machine address within the frame whose mapping to modify.
  *             The frame must belong to the FD, if one is specified.
  * val      -- Value to write into the mapping entry.
  *
- * ptr[1:0] == MMU_PT_UPDATE_PRESERVE_AD:
+ * ptr[2:0] == MMU_PT_UPDATE_PRESERVE_AD:
  * As MMU_NORMAL_PT_UPDATE above, but A/D bits currently in the PTE are ORed
  * with those in @val.
  *
- * ptr[1:0] == MMU_PT_UPDATE_NO_TRANSLATE:
+ * ptr[2:0] == MMU_PT_UPDATE_NO_TRANSLATE:
  * As MMU_NORMAL_PT_UPDATE above, but @val is not translated though FD
  * page tables.
  *
-- 
2.55.0



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