|
[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] Re: [PATCH v1 13/17] xen/riscv: add unprivileged guest memory read helper
On 8/18/26 10:17 AM, Jan Beulich wrote: On 17.08.2026 17:36, Oleksii Kurochko wrote:On 8/12/26 5:30 PM, Jan Beulich wrote:On 20.07.2026 18:02, Oleksii Kurochko wrote:Introduce riscv_vcpu_unpriv_read() to allow Xen to safely read guest memory using HLV/HLVX instructions while reliably capturing trap context.Both for the title and the function name: How does "unprivileged" matter here?Unprivileged because HLV/HLVX reads guest memory as if it were accessed from a less-privileged (guest) context, rather than by the hypervisor in HS mode. I think I am okay generally to drop "unpriv..." from the function name.The same functions would be use for reading Dom0's memory, wouldn't they?Yes, I don't see any issue to let this function to read DomO's memory too. But Dom0 could be counted as "unprivileged" too as it is executed in VS-mode which is less-privileged then HS-mode. I will use then guest.
Then I will use the option mentioned ...
... here.Probably I have to return '[addr] "r" (guest_addr)' to output and use +&r constraint. You also need to take precautions for not returning an uninitialized "val". I think the variable wants initializing (perhaps to ~0) and "+r" wants using as constraint. (Afaik & isn't necessary to use together with +.)I agree with '+' if we will initialize val with some value. Regarding, '&' my understanding is that I have to use it always whenWhen what exactly? If an operand is both input and output, how could the compiler re-use the (generally) register for any further purpose? '&' indicates to the compiler that it may not use the register used for an output to hold some input's value, as that value may be lost by the time the input is actually consumed. But what is written in the gcc doc:& - Means (in a particular alternative) that this operand is an earlyclobber operand, which is written before the instruction is finished using the input operands. What sounds like if an operand (val) in our case is written before the instruction which using the input operands (and after the write instuction which writes val there are instructions which are using input operands) it is needed to have &. t1: hlvx.hu %[val], (%[addr]) W:val R:addr + can trap -> read register ti t2: andi %[tmp], %[val], 3 W:tmp R:val t3: addi %[tmp], %[tmp], -3 t4: bnez %[tmp], 3f t5: addi %[addr], %[addr], 2 W:addr R:addrt6: hlvx.hu %[tmp], (%[addr]) W:tmp R:addr + can trap -> read register ti t7: slli %[tmp], %[tmp], 16 t8: or %[val], %[val], %[tmp] W:val So val is written on t1 before t6 where addr and ti still alive. The similar is for [addr] "+&r" (guest_addr):addr is written on t5 and input ti is alive till t6. So if allocator will allocate the same register for addr and ti then addi %[addr], %[addr], 2 will break a pointer and handler will get something wrong. Am I missing something? If I am still wrong then in both cases should be just "+r"? ~ Oleksii
|
![]() |
Lists.xenproject.org is hosted with RackSpace, monitoring our |