Re: [PATCH v3 14/22] x86/boot: choose AP stack based on APIC ID

[Jan Beulich <jbeulich@xxxxxxxx>]

On 30.06.2026 11:31, Sergii Dmytruk wrote:
> On Tue, Jun 30, 2026 at 09:17:59AM +0200, Jan Beulich wrote:
>> On 30.06.2026 00:18, Sergii Dmytruk wrote:
>>> On Thu, Jan 22, 2026 at 04:52:36PM +0100, Jan Beulich wrote:
>>>>> --- a/xen/arch/x86/boot/x86_64.S
>>>>> +++ b/xen/arch/x86/boot/x86_64.S
>>>>> @@ -15,7 +15,33 @@ ENTRY(__high_start)
>>>>>          mov     $XEN_MINIMAL_CR4,%rcx
>>>>>          mov     %rcx,%cr4
>>>>>
>>>>> -        mov     stack_start(%rip),%rsp
>>>>> +        test    %ebx,%ebx
>>>>> +        cmovz   stack_start(%rip), %rsp
>>>>> +        jz      .L_stack_set
>>>>> +
>>>>> +        /* APs only: get stack base from APIC ID saved in %esp. */
>>>>> +        mov     $-1, %rax
>>>>
>>>> Here and below 32-bit insn would do fine. However, ...
>>>
>>> Are all addresses guaraneed to be below 4 GiB?
>>
>> You use %rax as the loop induction variable, so there isn't any address
>> in it? Plus you already use ...
>>
>>>>> +        lea     x86_cpu_to_apicid(%rip), %rcx
>>>>> +1:
>>>>> +        add     $1, %rax
>>>>> +        cmp     $NR_CPUS, %eax
>>
>> ... as 32-bit insn here anyway.
> 
> But %rcx contains an address and it is added to %rax for `cmp` (quoted
> below).

Well, to use SCAS you will need to change how you use registers. (IOW
first you need to determine whether SCAS actually can be used here,
and then - if it can - you will need to arrange register use to fit it.)

>  Also if an address can be larger than 4 GiB, REPNE SCASL will
> have to be 64-bit which is incompatible with the lookup for a 32-bit
> value (unless I'm missing an instruction form that takes 64-bit address
> but compares 32-bit values).

Address size and operand size can be controlled independently. By
default the former is 64 bits, while the suffix ('L' here) indicates
the operand size wanted.

Jan