Re: [RFC PATCH] arm/gic: Optimize lr_mask type based on GIC version

[Julien Grall <julien@xxxxxxx>]

On 06/03/2026 10:09, Halder, Ayan Kumar wrote:
> Hi Jan,
>
> On 06/03/2026 08:49, Jan Beulich wrote:
> > On 05.03.2026 20:57, Ayan Kumar Halder wrote:
> > > --- a/xen/arch/arm/include/asm/gic.h
> > > +++ b/xen/arch/arm/include/asm/gic.h
> > > @@ -237,7 +237,15 @@ enum gic_version {
> > >       GIC_V3,
> > >   };
> > > +/*
> > > + * GICv3 supports up to 16 LRs (4 bits in ICH_VTR_EL2), can use 
> > > uint16_t
> > > + * GICv2 supports up to 64 LRs (6 bits in GICH_VTR), requires uint64_t
> > > + */
> > > +#ifdef CONFIG_GICV3
> > > +DECLARE_PER_CPU(uint16_t, lr_mask);
> > > +#else
> > >   DECLARE_PER_CPU(uint64_t, lr_mask);
> > > +#endif
> > But GICV2 and GICV3 can be enabled at the same time, at which point 
> > you'd still
> > need 64 bits, I suppose.
> I see. However, a safety certified Xen which is meant to support GICv3 
> hardware, will only have GICv3 enabled.
> IOW having both GICV2 =y && GICV2 = y is out of scope for the safety use 
> cases.
If the patch is indented to be merged in mainline Xen, then you need to 
support the case where both GICV2 = y && GICV3 = y.
If the patch is not intended to be merged in mainline then it should 
have been marked as such so we can adjust our review.
Cheers,

--
Julien Grall