Re: [PATCH] x86/cpu/intel: Limit the non-architectural constant_tsc model checks

[Roger Pau Monné <roger.pau@xxxxxxxxxx>]

On Fri, Feb 20, 2026 at 10:42:57AM +0000, Andrew Cooper wrote:
> From: Sohil Mehta <sohil.mehta@xxxxxxxxx>
> 
> X86_FEATURE_CONSTANT_TSC is a Linux-defined, synthesized feature flag.
> It is used across several vendors. Intel CPUs will set the feature when
> the architectural CPUID.80000007.EDX[1] bit is set. There are also some
> Intel CPUs that have the X86_FEATURE_CONSTANT_TSC behavior but don't
> enumerate it with the architectural bit.  Those currently have a model
> range check.
> 
> Today, virtually all of the CPUs that have the CPUID bit *also* match
> the "model >= 0x0e" check. This is confusing. Instead of an open-ended
> check, pick some models (INTEL_IVYBRIDGE and P4_WILLAMETTE) as the end
> of goofy CPUs that should enumerate the bit but don't.  These models are
> relatively arbitrary but conservative pick for this.
> 
> This makes it obvious that later CPUs (like Family 18+) no longer need
> to synthesize X86_FEATURE_CONSTANT_TSC.
> 
> Signed-off-by: Sohil Mehta <sohil.mehta@xxxxxxxxx>
> Signed-off-by: Ingo Molnar <mingo@xxxxxxxxxx>
> Link: https://lore.kernel.org/r/20250219184133.816753-14-sohil.mehta@xxxxxxxxx
> Link: https://git.kernel.org/tip/fadb6f569b10bf668677add876ed50586931b8f3
> [Port to Xen]
> Signed-off-by: Kevin Lampis <kevin.lampis@xxxxxxxxxx>
> Signed-off-by: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>

Acked-by: Roger Pau Monné <roger.pau@xxxxxxxxxx>

Thanks, Roger.