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Re: [PATCH 02/12] x86: Add more granularity to the vendors in Kconfig


  • To: Roger Pau Monné <roger.pau@xxxxxxxxxx>
  • From: Alejandro Vallejo <alejandro.garciavallejo@xxxxxxx>
  • Date: Tue, 10 Feb 2026 11:04:03 +0100
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  • Cc: <xen-devel@xxxxxxxxxxxxxxxxxxxx>, Jan Beulich <jbeulich@xxxxxxxx>, "Andrew Cooper" <andrew.cooper3@xxxxxxxxxx>, Jason Andryuk <jason.andryuk@xxxxxxx>
  • Delivery-date: Tue, 10 Feb 2026 10:04:29 +0000
  • List-id: Xen developer discussion <xen-devel.lists.xenproject.org>

On Tue Feb 10, 2026 at 9:26 AM CET, Roger Pau Monné wrote:
> On Fri, Feb 06, 2026 at 05:15:24PM +0100, Alejandro Vallejo wrote:
>> This enables very aggressive DCE passes on single-vendor builds in later
>> patches, as it will allow most vendor checks to become statically chosen
>> branches. A lot of statics go away and a lot more inlining will be allowed.
>> 
>> A prerequisite for such optimisation is to expand Kconfig to have the
>> full set of vendors. Adds Hygon, Centaur, Shanghai and the unknown-vendor
>> path. Have Hygon select AMD, and Centaur|Shanghai select Intel.
>> 
>> Not a functional change.
>> 
>> Signed-off-by: Alejandro Vallejo <alejandro.garciavallejo@xxxxxxx>
>> ---
>> rfc -> v1:
>>   * s/depends on/select/
>>   * s/UNKNOWN_CPU/UNKNOWN_CPU_VENDOR/
>>   * Removed "if unsure, say Y"
>> ---
>>  xen/arch/x86/Kconfig.cpu  | 43 +++++++++++++++++++++++++++++++++++++++
>>  xen/arch/x86/cpu/Makefile |  6 +++---
>>  2 files changed, 46 insertions(+), 3 deletions(-)
>> 
>> diff --git a/xen/arch/x86/Kconfig.cpu b/xen/arch/x86/Kconfig.cpu
>> index 5fb18db1aa..f895cfe97a 100644
>> --- a/xen/arch/x86/Kconfig.cpu
>> +++ b/xen/arch/x86/Kconfig.cpu
>> @@ -19,4 +19,47 @@ config INTEL
>>        May be turned off in builds targetting other vendors.  Otherwise,
>>        must be enabled for Xen to work suitably on Intel platforms.
>>  
>> +config HYGON
>> +    bool "Support Hygon CPUs"
>> +    select AMD
>> +    default y
>> +    help
>> +      Detection, tunings and quirks for Hygon platforms.
>> +
>> +      May be turned off in builds targetting other vendors.  Otherwise,
>> +      must be enabled for Xen to work suitably on Hygon platforms.
>> +
>> +
>> +config CENTAUR
>> +    bool "Support Centaur CPUs"
>> +    select INTEL
>> +    default y
>> +    help
>> +      Detection, tunings and quirks for Centaur platforms.
>> +
>> +      May be turned off in builds targetting other vendors.  Otherwise,
>> +      must be enabled for Xen to work suitably on Centaur platforms.
>> +
>> +config SHANGHAI
>> +    bool "Support Shanghai CPUs"
>> +    select INTEL
>> +    default y
>> +    help
>> +      Detection, tunings and quirks for Shanghai platforms.
>> +
>> +      May be turned off in builds targetting other vendors.  Otherwise,
>> +      must be enabled for Xen to work suitably on Shanghai platforms.
>> +
>> +config UNKNOWN_CPU_VENDOR
>> +    bool "Support unknown CPU vendors"
>> +    default y
>> +    help
>> +      This option prevents a panic on boot when the host CPU vendor isn't
>> +      supported by going into a legacy compatibility mode and not applying
>> +      any relevant tunings or quirks.
>> +
>> +      Not selecting this options while selecting multiple vendors doesn't 
>> have
>> +      any major effect on code size, but selecting a single vendor with this
>> +      option cleared produces a much smaller build.
>> +
>>  endmenu
>> diff --git a/xen/arch/x86/cpu/Makefile b/xen/arch/x86/cpu/Makefile
>> index 7cfe28b7ec..84b060aa41 100644
>> --- a/xen/arch/x86/cpu/Makefile
>> +++ b/xen/arch/x86/cpu/Makefile
>> @@ -3,13 +3,13 @@ obj-y += microcode/
>>  obj-y += mtrr/
>>  
>>  obj-y += amd.o
>> -obj-y += centaur.o
>> +obj-$(CONFIG_CENTAUR) += centaur.o
>
> Maybe I'm missing some context here, but I think this would break the
> build?
>
> cpu/centaur.c exports centaur_cpu_dev which is referenced from
> cpu/common.c, and I don't see you making that reference in
> cpu/common.c conditional to CONFIG_CENTAUR being defined?
>
> I think the same applies to Hygon and Shanghai.
>
> Thanks, Roger.

Hmm. Yes, these hunks go on the following patch for bisectability. They work due
to the AND operation at the switch condition.

Cheers,
Alejandro



 


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