[PATCH] x86/intel: Drop more cpuid_mask_* infrastructure

[Andrew Cooper <andrew.cooper3@xxxxxxxxxx>]

Despite removing references from the documentation, the Intel parts of CPUID
Masking were accidentally left behind and still active.

Intel CPUID Masking is even more niche than AMD masking, as the MSRs only
exist between Nehalem and SandyBridge, being fully replaced with CPUID
Faulting from IvyBridge onwards.

Fixes: 317051c2f032 ("x86/amd: Drop the cpuid_mask_* command line options")
Signed-off-by: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
---
CC: Jan Beulich <JBeulich@xxxxxxxx>
CC: Roger Pau Monné <roger.pau@xxxxxxxxxx>
---
 xen/arch/x86/cpu/common.c | 13 -------------
 xen/arch/x86/cpu/cpu.h    |  3 ---
 xen/arch/x86/cpu/intel.c  | 18 ++----------------
 3 files changed, 2 insertions(+), 32 deletions(-)

diff --git a/xen/arch/x86/cpu/common.c b/xen/arch/x86/cpu/common.c
index 37820a3a08ab..79573384ea38 100644
--- a/xen/arch/x86/cpu/common.c
+++ b/xen/arch/x86/cpu/common.c
@@ -31,19 +31,6 @@ bool __read_mostly opt_dom0_cpuid_faulting = true;
 bool opt_arat = true;
 boolean_param("arat", opt_arat);
 
-unsigned int opt_cpuid_mask_ecx = ~0u;
-integer_param("cpuid_mask_ecx", opt_cpuid_mask_ecx);
-unsigned int opt_cpuid_mask_edx = ~0u;
-integer_param("cpuid_mask_edx", opt_cpuid_mask_edx);
-
-unsigned int opt_cpuid_mask_xsave_eax = ~0u;
-integer_param("cpuid_mask_xsave_eax", opt_cpuid_mask_xsave_eax);
-
-unsigned int opt_cpuid_mask_ext_ecx = ~0u;
-integer_param("cpuid_mask_ext_ecx", opt_cpuid_mask_ext_ecx);
-unsigned int opt_cpuid_mask_ext_edx = ~0u;
-integer_param("cpuid_mask_ext_edx", opt_cpuid_mask_ext_edx);
-
 unsigned int __initdata expected_levelling_cap;
 unsigned int __read_mostly levelling_caps;
 
diff --git a/xen/arch/x86/cpu/cpu.h b/xen/arch/x86/cpu/cpu.h
index 8bed3f52490f..bbede57ab00d 100644
--- a/xen/arch/x86/cpu/cpu.h
+++ b/xen/arch/x86/cpu/cpu.h
@@ -12,9 +12,6 @@ extern const struct cpu_dev intel_cpu_dev, amd_cpu_dev, 
centaur_cpu_dev,
     shanghai_cpu_dev, hygon_cpu_dev;
 
 extern bool opt_arat;
-extern unsigned int opt_cpuid_mask_ecx, opt_cpuid_mask_edx;
-extern unsigned int opt_cpuid_mask_xsave_eax;
-extern unsigned int opt_cpuid_mask_ext_ecx, opt_cpuid_mask_ext_edx;
 
 extern int get_model_name(struct cpuinfo_x86 *c);
 extern void display_cacheinfo(struct cpuinfo_x86 *c);
diff --git a/xen/arch/x86/cpu/intel.c b/xen/arch/x86/cpu/intel.c
index b76797cb9a4a..284101e4ea4c 100644
--- a/xen/arch/x86/cpu/intel.c
+++ b/xen/arch/x86/cpu/intel.c
@@ -259,6 +259,8 @@ static const typeof(ctxt_switch_masking) 
__initconst_cf_clobber __used csm =
  */
 static void __init noinline intel_init_levelling(void)
 {
+       uint32_t eax, ecx, edx, tmp;
+
        /*
         * Intel Fam0f is old enough that probing for CPUID faulting support
         * introduces spurious #GP(0) when the appropriate MSRs are read,
@@ -275,13 +277,8 @@ static void __init noinline intel_init_levelling(void)
        probe_masking_msrs();
 
        if (msr_basic) {
-               uint32_t ecx, edx, tmp;
-
                cpuid(0x00000001, &tmp, &tmp, &ecx, &edx);
 
-               ecx &= opt_cpuid_mask_ecx;
-               edx &= opt_cpuid_mask_edx;
-
                /* Fast-forward bits - Must be set. */
                if (ecx & cpufeat_mask(X86_FEATURE_XSAVE))
                        ecx |= cpufeat_mask(X86_FEATURE_OSXSAVE);
@@ -291,23 +288,12 @@ static void __init noinline intel_init_levelling(void)
        }
 
        if (msr_ext) {
-               uint32_t ecx, edx, tmp;
-
                cpuid(0x80000001, &tmp, &tmp, &ecx, &edx);
-
-               ecx &= opt_cpuid_mask_ext_ecx;
-               edx &= opt_cpuid_mask_ext_edx;
-
                cpuidmask_defaults.e1cd &= ((u64)edx << 32) | ecx;
        }
 
        if (msr_xsave) {
-               uint32_t eax, tmp;
-
                cpuid_count(0x0000000d, 1, &eax, &tmp, &tmp, &tmp);
-
-               eax &= opt_cpuid_mask_xsave_eax;
-
                cpuidmask_defaults.Da1 &= (~0ULL << 32) | eax;
        }
 

base-commit: e80f4da85b29f888c0644749b0a4ab29a9f2f6ca
-- 
2.39.5