[PATCH] x86/intel: Resync intel-family.h

[Andrew Cooper <andrew.cooper3@xxxxxxxxxx>]

Signed-off-by: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
---
CC: Jan Beulich <JBeulich@xxxxxxxx>
CC: Roger Pau Monné <roger.pau@xxxxxxxxxx>
CC: Kevin Lampis <kevin.lampis@xxxxxxxxxx>

I'm unsure about the Intel CPU Core types, but it's probably better to keep
them than strip them from our copy.
---
 xen/arch/x86/include/asm/intel-family.h | 68 +++++++++++++++++++++----
 1 file changed, 57 insertions(+), 11 deletions(-)

diff --git a/xen/arch/x86/include/asm/intel-family.h 
b/xen/arch/x86/include/asm/intel-family.h
index d8c0bcc406de..cc3fb4cc471f 100644
--- a/xen/arch/x86/include/asm/intel-family.h
+++ b/xen/arch/x86/include/asm/intel-family.h
@@ -1,8 +1,8 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 /*
  * Snapshot from Linux:
- *   db4001f9cc32e3ef105a4e4f492d7d813b28292a
- *   x86/cpu/vfm: Delete all the *_FAM6_ CPU #defines
+ *   89216c9051ef6635f1514f8e0d2f9cd63b37a3b6
+ *   x86/cpu: Add/fix core comments for {Panther,Nova} Lake
  */
 #ifndef _ASM_X86_INTEL_FAMILY_H
 #define _ASM_X86_INTEL_FAMILY_H
@@ -50,7 +50,18 @@
 /* Wildcard match so X86_MATCH_VFM(ANY) works */
 #define INTEL_ANY                      IFM(X86_FAMILY_ANY, X86_MODEL_ANY)
 
+/* Family 5 */
+#define INTEL_FAM5_START               IFM(5, 0x00) /* Notational marker, also 
P5 A-step */
+#define INTEL_PENTIUM_75               IFM(5, 0x02) /* P54C */
+#define INTEL_PENTIUM_MMX              IFM(5, 0x04) /* P55C */
+#define INTEL_QUARK_X1000              IFM(5, 0x09) /* Quark X1000 SoC */
+
+/* Family 6, 18, 19 */
 #define INTEL_PENTIUM_PRO              IFM(6, 0x01)
+#define INTEL_PENTIUM_II_KLAMATH       IFM(6, 0x03)
+#define INTEL_PENTIUM_III_DESCHUTES    IFM(6, 0x05)
+#define INTEL_PENTIUM_III_TUALATIN     IFM(6, 0x0B)
+#define INTEL_PENTIUM_M_DOTHAN         IFM(6, 0x0D)
 
 #define INTEL_CORE_YONAH               IFM(6, 0x0E)
 
@@ -115,11 +126,15 @@
 
 #define INTEL_SAPPHIRERAPIDS_X         IFM(6, 0x8F) /* Golden Cove */
 
-#define INTEL_EMERALDRAPIDS_X          IFM(6, 0xCF)
+#define INTEL_EMERALDRAPIDS_X          IFM(6, 0xCF) /* Raptor Cove */
 
-#define INTEL_GRANITERAPIDS_X          IFM(6, 0xAD)
+#define INTEL_GRANITERAPIDS_X          IFM(6, 0xAD) /* Redwood Cove */
 #define INTEL_GRANITERAPIDS_D          IFM(6, 0xAE)
 
+#define INTEL_DIAMONDRAPIDS_X          IFM(19, 0x01) /* Panther Cove */
+
+#define INTEL_BARTLETTLAKE             IFM(6, 0xD7) /* Raptor Cove */
+
 /* "Hybrid" Processors (P-Core/E-Core) */
 
 #define INTEL_LAKEFIELD                        IFM(6, 0x8A) /* Sunny Cove / 
Tremont */
@@ -131,14 +146,21 @@
 #define INTEL_RAPTORLAKE_P             IFM(6, 0xBA)
 #define INTEL_RAPTORLAKE_S             IFM(6, 0xBF)
 
-#define INTEL_METEORLAKE               IFM(6, 0xAC)
+#define INTEL_METEORLAKE               IFM(6, 0xAC) /* Redwood Cove / 
Crestmont */
 #define INTEL_METEORLAKE_L             IFM(6, 0xAA)
 
-#define INTEL_ARROWLAKE_H              IFM(6, 0xC5)
+#define INTEL_ARROWLAKE_H              IFM(6, 0xC5) /* Lion Cove / Skymont */
 #define INTEL_ARROWLAKE                        IFM(6, 0xC6)
 #define INTEL_ARROWLAKE_U              IFM(6, 0xB5)
 
-#define INTEL_LUNARLAKE_M              IFM(6, 0xBD)
+#define INTEL_LUNARLAKE_M              IFM(6, 0xBD) /* Lion Cove / Skymont */
+
+#define INTEL_PANTHERLAKE_L            IFM(6, 0xCC) /* Cougar Cove / Darkmont 
*/
+
+#define INTEL_WILDCATLAKE_L            IFM(6, 0xD5)
+
+#define INTEL_NOVALAKE                 IFM(18, 0x01) /* Coyote Cove / Arctic 
Wolf */
+#define INTEL_NOVALAKE_L               IFM(18, 0x03) /* Coyote Cove / Arctic 
Wolf */
 
 /* "Small Core" Processors (Atom/E-Core) */
 
@@ -152,9 +174,9 @@
 #define INTEL_ATOM_SILVERMONT          IFM(6, 0x37) /* Bay Trail, Valleyview */
 #define INTEL_ATOM_SILVERMONT_D                IFM(6, 0x4D) /* Avaton, Rangely 
*/
 #define INTEL_ATOM_SILVERMONT_MID      IFM(6, 0x4A) /* Merriefield */
+#define INTEL_ATOM_SILVERMONT_MID2     IFM(6, 0x5A) /* Anniedale */
 
 #define INTEL_ATOM_AIRMONT             IFM(6, 0x4C) /* Cherry Trail, Braswell 
*/
-#define INTEL_ATOM_AIRMONT_MID         IFM(6, 0x5A) /* Moorefield */
 #define INTEL_ATOM_AIRMONT_NP          IFM(6, 0x75) /* Lightning Mountain */
 
 #define INTEL_ATOM_GOLDMONT            IFM(6, 0x5C) /* Apollo Lake */
@@ -179,8 +201,32 @@
 #define INTEL_XEON_PHI_KNL             IFM(6, 0x57) /* Knights Landing */
 #define INTEL_XEON_PHI_KNM             IFM(6, 0x85) /* Knights Mill */
 
-/* Family 5 */
-#define INTEL_FAM5_QUARK_X1000         0x09 /* Quark X1000 SoC */
-#define INTEL_QUARK_X1000              IFM(5, 0x09) /* Quark X1000 SoC */
+/* Notational marker denoting the last Family 6 model */
+#define INTEL_FAM6_LAST                        IFM(6, 0xFF)
+
+/* Family 15 - NetBurst */
+#define INTEL_P4_WILLAMETTE            IFM(15, 0x01) /* Also Xeon Foster */
+#define INTEL_P4_PRESCOTT              IFM(15, 0x03)
+#define INTEL_P4_PRESCOTT_2M           IFM(15, 0x04)
+#define INTEL_P4_CEDARMILL             IFM(15, 0x06) /* Also Xeon Dempsey */
+
+/*
+ * Intel CPU core types
+ *
+ * CPUID.1AH.EAX[31:0] uniquely identifies the microarchitecture
+ * of the core. Bits 31-24 indicates its core type (Core or Atom)
+ * and Bits [23:0] indicates the native model ID of the core.
+ * Core type and native model ID are defined in below enumerations.
+ */
+enum intel_cpu_type {
+       INTEL_CPU_TYPE_UNKNOWN,
+       INTEL_CPU_TYPE_ATOM = 0x20,
+       INTEL_CPU_TYPE_CORE = 0x40,
+};
+
+enum intel_native_id {
+       INTEL_ATOM_CMT_NATIVE_ID = 0x2,  /* Crestmont */
+       INTEL_ATOM_SKT_NATIVE_ID = 0x3,  /* Skymont */
+};
 
 #endif /* _ASM_X86_INTEL_FAMILY_H */

base-commit: bc23a49d13a30de06a961dfaccc4a19262fe9967
-- 
2.39.5