[PATCH v5 07/15] emul/ns16x50: implement FCR register (write-only)

[dmukhin@xxxxxxx]

From: Denis Mukhin <dmukhin@xxxxxxxx> 

Add emulation logic for FCR register.

Note, that does not hooks FIFO interrupt moderation to the FIFO management
code.

Signed-off-by: Denis Mukhin <dmukhin@xxxxxxxx>
---
Changes since v4:
- new patch
---
 xen/common/emul/vuart/ns16x50.c | 24 ++++++++++++++++++++++++
 1 file changed, 24 insertions(+)

diff --git a/xen/common/emul/vuart/ns16x50.c b/xen/common/emul/vuart/ns16x50.c
index efb2f4c6441c..65ca96dd8bd3 100644
--- a/xen/common/emul/vuart/ns16x50.c
+++ b/xen/common/emul/vuart/ns16x50.c
@@ -363,6 +363,30 @@ static int ns16x50_io_write8(
 
             break;
 
+        case UART_FCR: /* WO */
+            if ( val & UART_FCR_RESERVED0 )
+                ns16x50_warn(vdev, "FCR: attempt to set reserved bit: %x\n",
+                             UART_FCR_RESERVED0);
+
+            if ( val & UART_FCR_RESERVED1 )
+                ns16x50_warn(vdev, "FCR: attempt to set reserved bit: %x\n",
+                             UART_FCR_RESERVED1);
+
+            if ( val & UART_FCR_CLRX )
+                ns16x50_fifo_rx_reset(vdev);
+
+            if ( val & UART_FCR_CLTX )
+                ns16x50_fifo_tx_flush(vdev);
+
+            if ( val & UART_FCR_ENABLE )
+                val &= UART_FCR_ENABLE | UART_FCR_DMA | UART_FCR_TRG_MASK;
+            else
+                val = 0;
+
+            regs[UART_FCR] = val;
+
+            break;
+
         default:
             rc = -EINVAL;
             break;
-- 
2.51.0