Re: [PATCH] xen/arm: smmuv3: Add cache maintenance for non-coherent SMMU queues

[Julien Grall <julien@xxxxxxx>]

Hi,

On 06/08/2025 15:58, Dmytro Firsov wrote:
> According to the Arm SMMUv3 spec (ARM IHI 0070), a system may have
> SMMU(s) that is/are non-coherent to the PE (processing element). In such
> cases, memory accesses from the PE should be either non-cached or be
> augmented with manual cache maintenance. SMMU cache coherency is reported
> by bit 4 (COHACC) of the SMMU_IDR0 register and is already present in the
> Xen driver. However, the current implementation is not aware of cache
> maintenance for memory that is shared between the PE and non-coherent
> SMMUs. It contains dmam_alloc_coherent() function, that is added during
> Linux driver porting. But it is actually a wrapper for _xzalloc(), that
> returns normal writeback memory (which is OK for coherent SMMUs).
>
> During Xen bring-up on a system with non-coherent SMMUs, the driver did
> not work properly - the SMMU was not functional and halted initialization
> at the very beginning due to a timeout while waiting for CMD_SYNC
> completion:
>
>    (XEN) SMMUv3: /soc/iommu@fa000000: CMD_SYNC timeout
>    (XEN) SMMUv3: /soc/iommu@fa000000: CMD_SYNC timeout
>
> To properly handle such scenarios, add the non_coherent flag to the
> arm_smmu_queue struct. It is initialized using features reported by the
> SMMU HW and will be used for triggering cache clean/invalidate operations.
> This flag is not queue-specific (it is applicable to the whole SMMU), but
> adding it to arm_smmu_queue allows us to not change function signatures
> and simplify the patch (smmu->features, which contains the required flag,
> are not available in code parts that require cache maintenance).
>
> Signed-off-by: Dmytro Firsov <dmytro_firsov@xxxxxxxx>

With one remark below:

Reviewed-by: Julien Grall <jgrall@xxxxxxxxxx>


> diff --git a/xen/drivers/passthrough/arm/smmu-v3.h 
> b/xen/drivers/passthrough/arm/smmu-v3.h
> index f09048812c..db936b9bd4 100644
> --- a/xen/drivers/passthrough/arm/smmu-v3.h
> +++ b/xen/drivers/passthrough/arm/smmu-v3.h
> @@ -522,6 +522,13 @@ struct arm_smmu_queue {
>   
>   	u32 __iomem			*prod_reg;
>         u32 __iomem                     *cons_reg;
> +
> +       /*
> +        * According to SMMU spec section 3.16, some systems may have
> +        * SMMUs, that are non-coherent to PE (processing elements).
> +        * In such case manual cache management is needed.
> +        */
Please mention the specification version because section numbers are not 
stable. That said, I am not sure I see the value to mention the spec 
here. I think it would be sufficient to say:
"Is the memory access coherent?"


Cheers,

> +       bool                            non_coherent;
>   };
>   
>   struct arm_smmu_cmdq {
--
Julien Grall