[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [PATCH v7 1/8] vpci/header: Emulate extended capability list for dom0
- To: Jan Beulich <jbeulich@xxxxxxxx>
- From: "Chen, Jiqian" <Jiqian.Chen@xxxxxxx>
- Date: Wed, 9 Jul 2025 05:29:35 +0000
- Accept-language: en-US
- Arc-authentication-results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=amd.com; dmarc=pass action=none header.from=amd.com; dkim=pass header.d=amd.com; arc=none
- Arc-message-signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=Bo9LeadlGJqiQLbMFXYvkmr7/qCVtAAv4WiAP6eg3E4=; b=QU/kWQXXVwQ8BqQqaNjY1BKKofg7gTPGKCYI8DYhm0NwnkX3M+n4/AFJAJ7D5+GnTbXCVX+65+mMxolYYdvHM5ukjF70kpTjVdjQxbOmEA7NCr1C7B8+SW2WSoTfbD9Umu6tbE19JMDMu5KrI3pVUkY3Xg2gjmOgW+Yf50Er3wC9juwin+oB86wWaQmU8raqogKwP3AV+PZ1Wx076OPOkK2TMDvly/x/5pzczgOWKLG95cRW1YFfaph+dz244nHf+sfp6RSd+JULfsLYgl14IXTs+SSW5n7Ba7W+NLNM869IGkaWZPwL3WAIAhYofuhYZzw7NkBOALYv1+QNSYDXSg==
- Arc-seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=mIjgV96YeUczZa8RyHiQQt7cU5g+NZvVXJkYrt8nIYYVTeDcIFgvk77GsM9VUDj+uIK9pYQaMtrhZVlf4PZl+YtywWvK6VTTEVSjW6yHxlAt2Kf6eIkap6KV90JPdRvAFTlJ6nq5iXFiCUOPd3EPtrvTKHicWhs5Twt8A66+nxCjmS20LqkJ1e2guK19VXprXoplGAh/mVCXX8tLDz/qT42nF5RP6POjXtVXUd/w34OAZZ+08g1ornknmGR/KvUlG6sUgbPv+vtKu5ZB2m+c//mhAmaPf6TeOLaGmeear5Aetdlhos4tfOTc+Ct4GPHMmuWSDVh4/o/1bFdN23+8vA==
- Authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=amd.com;
- Cc: "Huang, Ray" <Ray.Huang@xxxxxxx>, Roger Pau Monné <roger.pau@xxxxxxxxxx>, "xen-devel@xxxxxxxxxxxxxxxxxxxx" <xen-devel@xxxxxxxxxxxxxxxxxxxx>, "Chen, Jiqian" <Jiqian.Chen@xxxxxxx>
- Delivery-date: Wed, 09 Jul 2025 05:29:47 +0000
- List-id: Xen developer discussion <xen-devel.lists.xenproject.org>
- Thread-index: AQHb7LJxCAe3dwZ41UCqlD5sc7if87QoStWAgAGGGIA=
- Thread-topic: [PATCH v7 1/8] vpci/header: Emulate extended capability list for dom0
On 2025/7/8 22:10, Jan Beulich wrote:
> On 04.07.2025 09:07, Jiqian Chen wrote:
>> --- a/xen/drivers/vpci/header.c
>> +++ b/xen/drivers/vpci/header.c
>> @@ -836,6 +836,39 @@ static int vpci_init_capability_list(struct pci_dev
>> *pdev)
>> PCI_STATUS_RSVDZ_MASK);
>> }
>>
>> +static int vpci_init_ext_capability_list(const struct pci_dev *pdev)
>> +{
>> + unsigned int pos = PCI_CFG_SPACE_SIZE;
>> +
>> + if ( !is_hardware_domain(pdev->domain) )
>> + /* Extended capabilities read as zero, write ignore for DomU */
>> + return vpci_add_register(pdev->vpci, vpci_read_val, NULL,
>> + pos, 4, (void *)0);
>> +
>> + do
>> + {
>> + uint32_t header = pci_conf_read32(pdev->sbdf, pos);
>> + int rc;
>> +
>> + rc = vpci_add_register(pdev->vpci, vpci_read_val, vpci_hw_write32,
>> + pos, 4, (void *)(uintptr_t)header);
>
> If it wasn't for this use of vpci_hw_write32(), I'd be happy to provide my
> R-b. But this continues to look bogus to me: What use is it to allow writes
> when Dom0 then can't read back any possible effect of such a write (in the
> unexpected event that some of the bits were indeed writable)?
Oh, I got your concern.
What do you think about updating the header value after writing to hardware in
write function?
Or you prefer to pass NULL here?
>
> Jan
--
Best regards,
Jiqian Chen.
|
