[PATCH v7 1/7] x86: suppress ERMS for internal use when MISC_ENABLE.FAST_STRING is clear

[Jan Beulich <jbeulich@xxxxxxxx>]

Before we start actually adjusting behavior when ERMS is available,
follow Linux commit 161ec53c702c ("x86, mem, intel: Initialize Enhanced
REP MOVSB/STOSB") and zap the CPUID-derived feature flag when the MSR
bit is clear.

Signed-off-by: Jan Beulich <jbeulich@xxxxxxxx>
---
TBD: While with the use of host_cpu_policy "cpuid=no-erms" now
     propagates to guest view, we've now lost the earlier "Don't extend
     the artificial clearing to guest view, though: Guests can take
     their own decision in this regard, as they can read (most of)
     MISC_ENABLE.".
---
v7: Use host_cpu_policy in guest_common_default_feature_adjustments().
    Change commentary.
v5: Correct guest_common_max_feature_adjustments() addition.
v4: Also adjust guest_common_max_feature_adjustments().
v3: New.

--- a/xen/arch/x86/cpu/intel.c
+++ b/xen/arch/x86/cpu/intel.c
@@ -366,8 +366,18 @@ static void cf_check early_init_intel(st
                paddr_bits = 36;
 
        if (c == &boot_cpu_data) {
+               uint64_t misc_enable;
+
                check_memory_type_self_snoop_errata();
 
+               /*
+                * If fast string is not enabled in IA32_MISC_ENABLE for any 
reason,
+                * clear the enhanced fast string CPU capability.
+                */
+               rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
+               if (!(misc_enable & MSR_IA32_MISC_ENABLE_FAST_STRING))
+                       setup_clear_cpu_cap(X86_FEATURE_ERMS);
+
                intel_init_levelling();
        }
 
--- a/xen/arch/x86/cpu-policy.c
+++ b/xen/arch/x86/cpu-policy.c
@@ -487,6 +487,12 @@ static void __init guest_common_max_feat
      */
     if ( test_bit(X86_FEATURE_RTM, fs) )
         __set_bit(X86_FEATURE_RTM_ALWAYS_ABORT, fs);
+
+    /*
+     * ERMS is a performance hint.  A VM which previously saw ERMS will
+     * function correctly when migrated here, even if ERMS isn't available.
+     */
+    __set_bit(X86_FEATURE_ERMS, fs);
 }
 
 static void __init guest_common_default_feature_adjustments(uint32_t *fs)
@@ -562,6 +568,13 @@ static void __init guest_common_default_
         __clear_bit(X86_FEATURE_RTM, fs);
         __set_bit(X86_FEATURE_RTM_ALWAYS_ABORT, fs);
     }
+
+    /*
+     * ERMS is a performance hint, so is set unconditionally in the max
+     * policy.  However, guests should default to the host setting.
+     */
+    if ( !host_cpu_policy.feat.erms )
+        __clear_bit(X86_FEATURE_ERMS, fs);
 }
 
 static void __init guest_common_feature_adjustments(uint32_t *fs)
--- a/xen/arch/x86/include/asm/msr-index.h
+++ b/xen/arch/x86/include/asm/msr-index.h
@@ -493,6 +493,7 @@
 #define MSR_IA32_THERM_INTERRUPT       0x0000019b
 #define MSR_IA32_THERM_STATUS          0x0000019c
 #define MSR_IA32_MISC_ENABLE           0x000001a0
+#define MSR_IA32_MISC_ENABLE_FAST_STRING  (1<<0)
 #define MSR_IA32_MISC_ENABLE_PERF_AVAIL   (1<<7)
 #define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL  (1<<11)
 #define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL (1<<12)